Memory Access Circuit Parallel Read Prefetching
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Solution Overview
Problem
Current memory technologies face inefficiencies due to increased waiting time and hardware costs associated with cache memory and memory bandwidth improvements, particularly when addressing and fetching data are not aligned, leading to performance decreases.
Innovation Solution
A memory device and operation method utilizing two static random access memories (SRAMs) and an accessing circuit that alternately maps reference addresses to actual addresses, enabling parallel read and prefetch operations to reduce read delays and eliminate alignment constraints, thereby improving processor performance without additional hardware costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cache memory is added to improve operating speed, then the waiting time decreases, but the area and cost increase
Solution Approach 1:
The memory device is divided into multiple memory blocks (first memory block, second memory block, etc.) that can be independently accessed. Each block has its own address space and can be read in parallel, effectively segmenting the memory access process to improve speed without requiring a large cache memory structure.
Solution Approach 2:
The patent introduces a block-level address mapping mechanism that maps reference addresses to actual memory block addresses. This dimensional transformation allows the processor to access memory blocks in parallel based on block numbers rather than sequential addresses, achieving high-speed access without additional cache hardware.
2Speed
If memory bandwidth is increased to read more data at a time, then the operating speed improves, but additional hardware is required increasing cost
Solution Approach 1:
The memory device uses a universal address mapping mechanism that handles both sequential reads and random reads through the same block-based architecture. The accessing circuit performs address translation and block selection for various access patterns, eliminating the need for separate hardware paths for different read scenarios.
Solution Approach 2:
The accessing circuit serves as an intermediary between the processor and the memory blocks. It receives reference addresses from the processor, translates them to actual memory block addresses, and coordinates parallel reads from multiple blocks. This intermediary layer enables high bandwidth access without requiring the processor to directly manage complex memory operations.
3Productivity
If addresses are not aligned with read words, then the read time and fetch time require additional periods, but the performance decreases
Solution Approach 1:
The system performs preliminary block selection and address translation before the actual data read operation. By determining which memory blocks need to be read in advance and preparing the block addresses, the system eliminates alignment delays and ensures that data is ready for immediate transfer to the processor.
Solution Approach 2:
The address mapping mechanism dynamically adapts to different access patterns by translating reference addresses to appropriate memory block addresses in real-time. The accessing circuit adjusts the block selection and read timing based on the current access requirements, eliminating fixed alignment constraints and reducing read delays for non-aligned addresses.
Data Source
AI summary
A device is provided that includes a first memory and a second memory and an accessing circuit. Actual addresses of the first memory and the second memory alternately correspond to reference addresses of a processing circuit. The accessing circuit is configured to perform the steps outlined below. A read command corresponding to a reference read address is received from the processing circuit to convert the reference read address to an actual read address of the first memory and the second memory. A first read data is read from a first one of the first memory and the second memory according to the actual read address and a second read data is prefetched from a second one of the first memory and a second memory according to a next first read address simultaneously.