Dual Map Table Structure for Memory Controller Address Mapping
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Solution Overview
Problem
As data storage capacity increases in memory systems, the size of map tables and map caches also grows, leading to increased management costs and reduced efficiency in addressing logical to physical address mappings, which affects read and program performance.
Innovation Solution
Implementing a memory system with a dual map table structure where the second map table has N times the physical address region size of the first, allowing for group map entries to be added and erasing individual entries from the first table, and optimizing cache loading and search methods to improve efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the data storage capacity of the memory system increases, then the storage capacity is improved, but the size of map tables and map cache increases leading to increased management cost
Solution Approach 1:
The patent divides the map table into multiple segments (first map table and second map table) with different entry sizes. The first map table stores map entries with smaller physical address regions, while the second map table stores map entries with larger physical address regions (N times larger). This segmentation allows the system to efficiently manage large storage capacities without requiring uniformly large map table entries, thereby reducing overall management complexity and cost.
2Quantity of substance
If the size of map tables increases, then the storage capacity is improved, but the efficiency of accessing map tables decreases
Solution Approach 1:
The patent applies local quality by making different parts of the map table structure have different characteristics. The first map table uses smaller map entries suitable for fine-grained address mappings, while the second map table uses larger map entries for coarse-grained mappings. This allows the system to optimize access efficiency for different types of address translation needs, improving overall access speed despite increased map table size.
3Area of stationary object
If the physical address region size per map entry in the second map table is N times larger than in the first map table, then the coverage of address region is improved, but the precision of address mapping is reduced
Solution Approach 1:
The patent segments the address mapping function into two levels: the first map table provides precise mapping for smaller address regions, while the second map table provides broader coverage for larger address regions. By using both map tables together, the system achieves both wide address region coverage and precise address mapping, resolving the contradiction between coverage and precision.
Data Source
AI summary
A memory system, a memory controller and an operating method thereof, capable of reducing the storage capacity of data in relation with map tables, by, in the case where N map entries respectively corresponding to N consecutive physical address regions exist among map entries included in a first map table in a memory device, adding a group map entry indicating a mapping information corresponding to the group of the N number of consecutive physical address regions, to a second map table included in the memory device.