Flash Memory Wear Leveling via Bit Error Rate Estimation

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Solution Overview

Problem

Conventional flash memory devices face challenges in evenly distributing wear across blocks, leading to premature failure due to uneven write cycles, as they rely solely on erased counts for wear leveling, which is not a reliable indicator of block wear.

Innovation Solution

The method involves accessing and comparing bit error rate probabilities of free blocks to select the one with the lower error rate for erasing, and determining the type of data to store based on data type and block age, using bit error probability as an indicator of block condition.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If wear leveling is performed based on erased count, then block selection for erasing is simplified, but wear distribution becomes uneven and blocks fail prematurely

Engineering Contradiction:
Improveblock selection simplicityVSAvoidwear distribution effectiveness
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent changes the parameter used for wear leveling from erased count to bit error rate (BER). Instead of selecting blocks based on how many times they have been erased, the system estimates BER by reading data from candidate blocks and uses this more accurate reliability metric to guide block selection for erasing and data placement

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent replaces the simple counter-based mechanical tracking system (erased count) with a more sophisticated electronic measurement system that estimates bit error rate through actual data reads and error analysis, providing a more accurate representation of block wear and reliability

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Ease of manufacture

If blocks are selected for erasing based on lowest erased count, then implementation is straightforward, but blocks with higher actual error rates may be selected leading to premature failure

Engineering Contradiction:
Improveimplementation complexityVSAvoidblock lifespan
Core Design Contradiction:
Ease of manufactureVSDuration of action of stationary object

Solution Approach 1:

The patent performs preliminary bit error rate estimation on candidate blocks before selecting them for erasing or data placement. By reading data from candidate blocks and estimating BER in advance, the system identifies blocks with actually higher error rates and avoids selecting them, thereby extending block lifespan

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system implements feedback by continuously monitoring and estimating bit error rates of blocks, using this information to dynamically adjust block selection for erasing and data placement, and updating the BER estimates over time to reflect changing block conditions

Inventive Principle:
Principle #23Feedback

3Device complexity

If all data is treated uniformly without considering block condition, then data management is simplified, but critical data may be placed on deteriorating blocks

Engineering Contradiction:
Improvedata management complexityVSAvoiddata storage reliability
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent applies local quality by differentiating data management based on block condition. Instead of treating all blocks uniformly, the system estimates BER for each block and uses this information to make localized decisions about where to place different types of data, ensuring critical data goes to more reliable blocks

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the parameter guiding data placement from uniform allocation to BER-based allocation. By estimating bit error rates and using these values to determine data placement strategy, the system ensures that data, especially critical data, is stored on blocks with lower error rates and better reliability

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS9361167B2Bit error rate estimation for wear leveling and for block selection based on data type
Publication Date: 2016.06.07 SANDISK TECHNOLOGIES LLC
  • US9361167B2 patent drawing
  • US9361167B2 patent drawing
  • US9361167B2 patent drawing

AI summary

A method and system for wear balancing in a flash memory device using bit error probability is disclosed. The flash memory device includes blocks with different life spans, leading potentially to one block wearing out before the other. In order to avoid this, a controller is configured to determine a bit error probability of a block and determine, based on the bit error probability, whether to select the block for storage of data. A method and system for selecting a block in a flash memory device based on the type of data is disclosed. The type of data may comprise flash management data (which may be used to manage the flash memory device) and host data. An indication of age associated with the block (such as bit error probability) is analyzed in order to determine whether to store the data in the block based on the type of data.