Decoupled PCB Layout for Parallel GaN Switching Legs
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Solution Overview
Problem
Existing power switching circuits with parallel GaN devices face challenges such as increased parasitic capacitances and inductances, leading to electromagnetic interference, current oscillations, and voltage overshoots, which can impair or damage the GaN devices.
Innovation Solution
The proposed electrical-converter system incorporates a PCB structure where each switching leg of the power switching circuit maintains independent conduction paths, achieved by optimizing the distances and inductances between GaN devices, thereby minimizing parasitic inductances and enhancing dynamic current sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If parallel GaN devices are used to increase power handling capability, then power conversion capacity is improved, but parasitic capacitances and inductances increase leading to electromagnetic interference and current oscillations
Solution Approach 1:
The patent divides the power switching circuit into separate switching legs, each with independent conduction paths. This segmentation isolates the parasitic effects to individual legs rather than having them interact across the entire parallel structure, reducing electromagnetic interference and current oscillations while maintaining the power handling capability through parallel operation.
Solution Approach 2:
The patent optimizes the PCB layout to create asymmetric conduction path lengths, where each switching leg has specifically tailored trace lengths and via configurations. This local optimization minimizes parasitic inductances in critical paths while maintaining overall circuit performance, directly addressing the harmful effects of parasitic elements in parallel GaN device configurations.
2Device complexity
If conventional PCB layouts are used with parallel power devices, then device integration is improved, but voltage overshoots and current oscillations occur due to parasitic inductances
Solution Approach 1:
The patent deliberately creates asymmetric conduction paths with different lengths for different switching legs. This asymmetry is designed to balance the overall parasitic inductances across parallel legs by compensating for variations in device characteristics, thereby reducing voltage overshoots and current oscillations while maintaining effective device integration on the PCB.
Solution Approach 2:
The patent utilizes multi-layer PCB construction to route conduction paths through different layers and spatial dimensions. By optimizing the three-dimensional layout including via placements and trace routing across multiple layers, the design minimizes parasitic inductances without increasing planar footprint, achieving reliable voltage control while maintaining compact integration.
Data Source
AI summary
According to one aspect, embodiments of the invention provide an electrical-converter system comprising a printed circuit board including at least a first layer and a second layer, a switching node disposed on the second layer, a first transistor, a second transistor, a third transistor, and a fourth transistor disposed on the first layer, a first conduction path from a source of the first transistor, through the switching node, to a drain of the fourth transistor, the first conduction path having a first length, and a second conduction path from the source of the first transistor, through the switching node, to a drain of the second transistor, the second conduction path having a second length, wherein the first length of the first conduction path is greater than the second length of the second conduction path.