Decoupled Read Circuit for Compute-in-Memory Sense Amplifiers
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Solution Overview
Problem
In compute-in-memory systems, the shared use of column select lines for reading and writing memory cells leads to interference, causing bit flipping and reliability issues due to residual voltages on input/output lines, which affect the accuracy of sense amplifier readings.
Innovation Solution
The implementation of a read circuit decoupled from the sense amplifier's write function, allowing for separate control of read and write operations, thereby maintaining the integrity of sense amplifier voltages and enabling direct output to analog-to-digital converters or CIM circuits without transferring voltages to a secondary sense amplifier.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If column select lines are shared for both reading and writing memory cells, then device complexity is reduced, but reliability deteriorates due to interference and residual voltages causing bit flipping
Solution Approach 1:
The patent divides the column select function into separate read column select lines (RC0-RC3) and write column select lines (WC0-WC3), physically segmenting the control signals to eliminate interference between read and write operations while maintaining separate dedicated pathways for each function
Solution Approach 2:
The patent introduces a secondary sense amplifier as an intermediary component that receives voltages from the first sense amplifier and transfers them to output lines, isolating the primary sense amplifier from output disturbances and preventing residual voltages from affecting memory cell states
2Device complexity
If sense amplifier voltages are transferred to a secondary sense amplifier for output, then device integration is improved, but measurement precision deteriorates due to voltage disturbances and interference during transfer
Solution Approach 1:
The secondary sense amplifier acts as an intermediary that receives and transfers voltages without disturbing the primary sense amplifier operation, isolating the measurement process from output transfer disturbances and maintaining voltage accuracy throughout the signal path
Solution Approach 2:
The patent extracts the output transfer function from the primary sense amplifier by routing voltages through the secondary sense amplifier, separating the sensitive measurement function from the potentially disruptive transfer operation to preserve measurement precision
3Ease of operation
If read and write operations share the same control lines, then ease of operation is improved, but reliability worsens due to residual voltages affecting memory cell states
Solution Approach 1:
The patent segments control lines into dedicated read column select lines and write column select lines, allowing independent control of read and write operations without interference, while maintaining separate signal pathways for each operation type
Solution Approach 2:
Instead of sharing control lines and managing interference, the patent inverts the approach by providing separate control lines for read and write operations, eliminating the need for complex interference management while improving reliability
Data Source
AI summary
A memory device including a memory array configured to store data, a senseamplifier circuit coupled to the memory array, and a read circuit coupled to the sense amplifier circuit, wherein the read circuit includes a first input that receives a read column select signal for activating the read circuit to read the data out of the memory array through the read circuit during a read operation.