Decoupling Capacitor Charge Preservation in Low Power Logic Circuits
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Solution Overview
Problem
Dynamic Voltage and Frequency Scaling (DVFS) systems in System-on-Chips (SoCs) face inefficiencies in low power modes due to energy losses from charging and discharging large decoupling capacitors, which are not fully discharged to the minimum voltage required for retention, leading to increased power consumption and longer wake-up times.
Innovation Solution
Implementing a low power voltage regulator and control circuit that selectively applies a lower regulated voltage during low power modes, decoupling the decoupling capacitor from the logic circuit, and using a Switched Capacitor Power Converter (SCPC) to minimize energy loss and preserve charge, allowing for faster wake-up and reduced power wastage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If DVFS is used to lower supply voltage during low power modes, then power consumption is reduced, but decoupling capacitors are not fully discharged leading to energy waste and longer wake-up times
Solution Approach 1:
The patent applies preliminary action by proactively discharging decoupling capacitors to the minimum retention voltage before the SoC enters low power mode, rather than allowing them to retain higher voltages. This preliminary discharge action prevents the waste of energy that would otherwise be consumed during wake-up when capacitors need to be recharged, thus resolving the contradiction between reducing power consumption and avoiding energy waste.
2Speed
If decoupling capacitors are maintained at higher voltage during low power mode, then faster wake-up is achieved, but power consumption increases
Solution Approach 1:
The patent performs the discharge of decoupling capacitors in advance before low power mode entry, so that during low power mode the capacitors remain at minimum retention voltage. When wake-up is needed, the capacitors can be rapidly recharged from this known baseline state, achieving fast wake-up without maintaining high voltage (and thus high power consumption) during the low power mode itself.
Solution Approach 2:
The patent implements dynamic voltage management by transitioning decoupling capacitor voltages between two states: minimum retention voltage during low power mode and higher voltage during active mode. This dynamic adjustment allows the system to optimize for power consumption during low power mode while maintaining the capability for fast wake-up when voltage is restored, resolving the contradiction between speed and energy usage.
3Loss of energy
If decoupling capacitors are fully discharged to minimum voltage, then energy waste is reduced, but wake-up time increases
Solution Approach 1:
The patent applies preliminary action by discharging capacitors to the minimum retention voltage before low power mode entry, establishing an optimal baseline state. This preliminary discharge minimizes energy waste during low power mode while creating a known starting point for rapid recharging during wake-up, thus avoiding the trade-off between energy waste and wake-up time.
Solution Approach 2:
The patent implements periodic voltage management where decoupling capacitors are discharged to minimum retention voltage periodically (before low power mode) and then rapidly recharged when needed (during wake-up). This periodic action pattern allows the system to minimize energy waste during low power operation while maintaining fast wake-up capability through scheduled preparation and rapid restoration cycles.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces overall energy expenditure during mode transitions and maintains the decoupling capacitor's charge, enabling faster wake-up and lower power consumption, particularly beneficial for battery-operated devices like wearables.
Implementation Method 1
Preserving a decoupling capacitor's charge during low power operation of a logic circuit
Data Source
AI summary
Systems and methods for preserving a decoupling capacitor's charge during low power operation of a logic circuit. An electronic circuit may include: a main voltage regulator coupled to a supply voltage terminal and configured to apply a first regulated voltage across a capacitor coupled in parallel with a logic circuit; a low power regulator coupled to the supply voltage terminal and configured to apply a second regulated voltage across the logic circuit; and a control circuit coupled to the low power regulator. The control circuit may be configured to: during a first mode of operation, allow the main voltage regulator to apply the first regulated voltage to the logic circuit, and, during a second mode of operation, allow the low power regulator to apply the second regulated voltage to the logic circuit and decouple the capacitor from the logic circuit while the low power regulator applies the second regulator voltage.