Decoupling Circuit Charge Sharing for Memory Plane Sensing
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Solution Overview
Problem
Non-volatile memory devices face challenges in reducing sensing variations across different planes, leading to inconsistent performance due to varying transition times during precharge and bit line voltage develop stages.
Innovation Solution
Incorporating a decoupling circuit with at least one decoupling capacitor that executes charge sharing via a first node, maintaining constant transition time differences between planes during these stages, thereby reducing sensing variations and enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple planes are used in the memory cell array, then storage capacity is improved, but sensing variations between planes increase due to different transition times
Solution Approach 1:
A decoupling circuit is introduced as an intermediary component between the bit line and the page buffer. This decoupling circuit includes a decoupling capacitor that is connected to a first node, which is positioned between the page buffer and the decoupling circuit. The decoupling circuit executes charge sharing via the first node to maintain constant transition times for bit line voltage control signals across different planes, thereby reducing sensing variations while preserving the multi-plane storage capacity.
2Measurement precision
If decoupling circuit is added to reduce sensing variations, then sensing accuracy is improved, but device complexity increases
Solution Approach 1:
The decoupling circuit is segmented and specifically positioned at strategic locations within the memory device architecture. Rather than adding decoupling circuits to all planes uniformly, the patent places decoupling circuits at specific nodes where they can most effectively influence the bit line voltage control signals. This segmented approach reduces sensing variations while minimizing the overall increase in device complexity.
3Speed
If transition time is reduced for faster sensing, then speed is improved, but voltage stability during precharge and develop stages deteriorates
Solution Approach 1:
The decoupling circuit operates in a periodic manner, executing charge sharing at specific intervals during the sensing process. The decoupling capacitor charges and discharges in synchronization with the precharge and develop stages, providing periodic voltage stabilization. This periodic action allows for faster transition times while maintaining voltage stability during critical sensing phases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The decoupling circuit ensures consistent voltage transitions across all planes, reducing sensing variations and improving the overall performance of non-volatile memory devices by maintaining constant transition times, thus enhancing data sensing capabilities.
Implementation Method 1
The decoupling circuit includes at least one decoupling capacitor and is configured to execute charge sharing via the first node
Data Source
AI summary
A non-volatile memory device may include a memory cell array including a plurality of planes, a page buffer connected to the memory cell array and corresponding to each of the plurality of planes, and a decoupling circuit. The page buffer is configured to receive a bit line voltage control signal (BLSHF) via a first node. The decoupling circuit is connected to the first node. The decoupling circuit includes at least one decoupling capacitor configured to execute charge sharing via the first node.