Read-Only Memories TRIZ Cases

Pointer-based page selection eliminates address conversion tables and resolves block-page ambiguity in multi-bit flash memory systems.

An SSD controller generates soft-decision metrics from channel parameters during a single hard decode read operation.

A control circuit compares memory cell threshold voltages against reference levels to identify cells requiring refresh operations.

Segmenting memory blocks into independent strings allows selective erasure without data migration, reducing total erasing time while maintaining data retention.

A dual calibration scheme calculates independent read voltage offset values to optimize memory access speed.

A memory system dynamically adjusts active loads to maintain stable programming voltage during write operations.

Discharging the source line through the memory cell enables concurrent program verification of multiple data states without requiring negative read voltages.

Peripheral circuit detects changed bits across multiple test voltages to determine optimal read voltage for semiconductor memory devices.

A nonvolatile memory erase method adjusts effective erasing times for individual word lines based on measured operation speeds.

Precharging sense nodes compensates for parasitic capacitance-induced voltage loss, preventing read errors in high-density flash memory devices.

Reverse reading identifies incorrectly programmed memory cells caused by source terminal noise, enabling targeted second programming to ensure data accuracy.

A flash memory data writing method directs write operations to strong pages within target pair blocks.

Merging N-well regions eliminates isolation portions to reduce area occupancy while maintaining processing accuracy through shared substrate contacts.

An eFUSE circuit records stress application status to trigger a switch control part that isolates power, preventing over-stress damage during retesting.

Peripheral circuits apply dynamic bit line voltages to selected memory cells, narrowing threshold voltage distribution and improving programming precision.

Segmenting program verify levels allows dynamic pulse adjustment, preventing overprogramming of fast cells and improving reliability.

Applying a lower second negative reference voltage identifies deep-erase cells with sub-zero threshold voltages, reducing circuit burden.

A flash controller trains a deep neural network to predict threshold voltage shift offset values for outlier blocks.

A sense module array isolates noise from locked-out cells using voltage boosting and transfer gates, preventing interference with active sensing operations.

Hierarchical bitline structure with split substrate select gates isolates local bitlines from global lines during erase operations.

A memory controller estimates threshold voltages using adjacent cell detection to reproduce user data accurately.

A defective address processing circuit compares initial target and non-target address information to output valid unique addresses.

An internal voltage generation circuit uses an integration circuit to produce an initial voltage with a constant slope.

A memory device uses division clock signals to sample command and address data for reliable transmission.

Staggered precharge activation signals reduce peak current and equalize write times across semiconductor memory banks.

Adaptive re-write corrects errors detected by post-write read, reducing ECC complexity and improving performance.

Control circuit adjusts sense-node charging time to set flexible current thresholds for accurate 0-margin testing of defective anti-fuse cells.

A memory program circuit fills buffer gaps with existing sector data to enable single-command programming operations.

Segmented MOS transistor discharge units reduce bit line discharge time by mitigating parasitic resistance and capacitance in phase-change random access memory.

An operation method adjusts programming and reading levels based on the second storage position state in non-volatile memory cells.

A voltage generator circuit uses reference cells with accessible floating gates to produce a stable reference voltage.

A semiconductor device stores state codes during pause commands to resume erase operations from specific periods.

Dummy cells detect uneven leakage current in nonvolatile memory devices, allowing a bias circuit to adjust voltages and stabilize operational reliability.

A non-volatile memory sensing circuit uses current mirrors and switches to generate reference and sensed currents for accurate state determination.

Series-connected medium voltage transistors in the row selector reduce chip area and manufacturing complexity while maintaining required voltage handling.

Synchronizing the sense operation with a clock signal prevents power supply noise from corrupting read data during output driver switching.

An input buffer uses a feedback circuit with a variable resistor and inverter to prevent signal amplitude decrease during high-speed operation.

A decoupling circuit executes charge sharing via a first node to stabilize bit line voltage transitions across memory planes.

A high voltage transfer switch circuit uses optimized E-type transistor impurity densities to enhance current driving capability.

Fuse controller initializes fuse data via boot-up signals, resolving clock phase misalignment errors during high-speed semiconductor startup.

An oxide semiconductor writing transistor holds charge at a node without high voltage, eliminating frequent refresh operations and reducing power consumption.

Memory circuitry dynamically raises sense current upon program operation thresholds to counteract leakage-induced sensing errors.

A memory system programs dummy data to storage areas based on erase program intervals.

A current-mode programmable reference circuit uses floating-gate transistors and differential amplifiers to generate stable reference currents.

A flash memory block erasing method applies targeted erase pulses only to rows containing unerased cells.

An encoder performs XOR operations on input data and random word line data to minimize back pattern dependency errors in multi-level cell flash memory.

An A/D converter monitors internal voltages in a non-volatile storage device to detect data retention faults and prevent irregular errors.

Switches between fast and precision verification methods during program-verify loops to resolve threshold voltage distribution overlaps.

A semiconductor memory device uses dual-level data reading to detect retention status via arithmetic comparison.