Semiconductor Switch Circuit Reducing Hot Carrier Degradation
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Solution Overview
Problem
Existing semiconductor devices face challenges in transferring high voltages efficiently while maintaining reliability and preventing increases in circuit area, particularly in NAND-type non-volatile memory systems where high voltage switches experience reliability deterioration due to hot carrier generation and resistance variations in diffusion layers.
Innovation Solution
The semiconductor device incorporates a high voltage transfer switch circuit with a specific configuration of D-type and E-type transistors, where the E-type transistor has a gate insulating film thickness between 13 nm to 50 nm and impurity densities optimized for threshold control, and the wiring structure is extended to cover the diffusion layers, reducing resistance variations and hot carrier generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high voltage transfer switch circuit is used to transfer 15V or more to memory cells, then writing and erasing operations can be performed, but hot carrier generation occurs causing reliability deterioration
Solution Approach 1:
The patent changes the gate insulating film thickness parameter to a specific range (5nm to 20nm) to reduce hot carrier generation while maintaining the high voltage transfer capability. This parameter optimization directly addresses the reliability issue by controlling the physical dimensions that influence carrier behavior under high voltage stress.
Solution Approach 2:
The patent applies different impurity densities to different regions of the transistor (first impurity density in the channel region, second impurity density in the drain region) to locally optimize performance. This local quality differentiation reduces hot carrier generation in critical areas while maintaining overall switch functionality for high voltage transfer.
2Reliability
If the gate insulating film thickness is reduced to minimize hot carrier generation, then reliability improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent specifies a gate insulating film thickness range of 5nm to 20nm that balances hot carrier reduction with manufacturability. This parameter selection achieves reliability improvement while remaining within practical manufacturing capabilities, avoiding excessive precision requirements.
Solution Approach 2:
The patent differentiates impurity densities in different regions to compensate for variations introduced by thin film manufacturing. The localized impurity control provides tolerance to film thickness variations, reducing the impact of manufacturing precision limitations.
3Ease of operation
If impurity density is increased to control threshold voltage, then switching performance improves, but resistance variation in diffusion layers increases
Solution Approach 1:
The patent applies different impurity densities to different regions: a first impurity density in the channel region for threshold control and a second impurity density in the drain region for stability. This localized differentiation allows threshold voltage control while minimizing resistance variation in the diffusion layers.
Solution Approach 2:
The patent segments the impurity distribution into distinct regions with different concentrations, separating the functions of threshold control and resistance stabilization. This segmentation allows independent optimization of each function without compromising the other.
4Productivity
If circuit area is kept small to increase integration density, then productivity improves, but heat dissipation becomes more difficult
Solution Approach 1:
The patent optimizes the gate insulating film thickness to reduce hot carrier generation, which directly reduces heat generation in the switch circuit. This parameter change enables high integration density while managing heat dissipation constraints through reduced thermal load per device.
Solution Approach 2:
The patent creates localized regions with different impurity densities to optimize current distribution and reduce hot spots. This local quality control improves heat dissipation efficiency within the compact circuit area by preventing concentrated thermal loading.
Data Source
AI summary
A switch element configured to apply a voltage to and block a voltage from a gate electrode of a memory cell is provided. The E-type transistor includes a gate insulating film with a thickness in a range of 13 nm to 50 nm, a first current terminal, and a second current terminal. The E-type transistor includes a first source diffusion layer and a first drain diffusion layer having a first n-type impurity density and formed in a vicinity of the gate electrode; and a second source diffusion layer and a second drain diffusion layer having a second n-type impurity density higher than the first n-type impurity density. The second current terminal of the E-type transistor is electrically connected to a voltage source configured to provide a voltage equal to or larger than 15 V.