Semiconductor Device Deep-Erase Verification Circuit
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Solution Overview
Problem
Existing semiconductor devices face reliability issues due to deep-erase cells, which have threshold voltages lower than 0 V, and there is a need for an effective method to identify and manage these cells.
Innovation Solution
A semiconductor device is designed with a peripheral circuit that performs a deep-erase verification operation by applying a second negative reference voltage lower than the first negative reference voltage to target memory cells, determining whether they are deep-erase cells with threshold voltages lower than the first negative reference voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a first negative reference voltage is applied to verify deep-erase cells, then measurement precision for identifying deep-erase cells is improved, but device complexity increases due to requiring multiple reference voltage levels
Solution Approach 1:
The patent changes the voltage parameter by applying a second negative reference voltage that is lower than the first negative reference voltage during the deep-erase verification operation. This parameter change allows the circuit to identify deep-erase cells with threshold voltages lower than the first negative reference voltage, improving measurement precision while using a manageable voltage level strategy rather than requiring multiple complex reference voltage generators
Solution Approach 2:
The patent applies a second negative reference voltage that is lower than the first negative reference voltage, which is an excessive action beyond the standard verification voltage. This allows the circuit to definitively identify deep-erase cells by comparing against a more stringent voltage threshold, ensuring that cells with extremely low threshold voltages are caught without requiring a full spectrum of reference voltage levels
2Reliability
If multiple reference voltages are generated and stored in the circuit, then reliability of deep-erase cell management is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses parameter changes by dynamically selecting different voltage levels (first negative reference voltage and second negative reference voltage) based on the verification needs. This approach maintains reliability by adapting the voltage parameter to the specific verification requirement while avoiding the need for multiple precisely-matched reference voltage generators, thereby reducing manufacturing precision requirements
3Measurement precision
If a second negative reference voltage lower than the first negative reference voltage is applied, then deep-erase cell detection capability is improved, but energy consumption increases
Solution Approach 1:
The patent implements periodic action by applying the second negative reference voltage only during specific deep-erase verification operations rather than continuously. This allows the system to maintain high detection capability when needed while minimizing energy consumption during normal operations, as the lower voltage level is used selectively for verification rather than being constantly applied
Data Source
AI summary
A semiconductor device includes a memory cell array and a peripheral circuit. The memory cell array is coupled to a plurality of word lines and a plurality of bit lines. The peripheral circuit performs a deep-erase verification operation to determine whether a target memory cell has a threshold voltage that is lower than a first negative reference voltage by applying a second negative reference voltage that is lower than the first negative reference voltage to the target memory cell.