Semiconductor Memory Data Retention Detection and Migration
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Solution Overview
Problem
Data retention issues in semiconductor memory devices, such as NAND flash memory, lead to data deterioration and destruction due to electron leakage or injection into floating gates, causing threshold value fluctuations, which existing technologies fail to effectively address.
Innovation Solution
A semiconductor memory device and control method that includes a memory cell array, data latch circuits, an arithmetic circuit, and a controller to read data at different voltage levels, perform arithmetic operations, count differences, and output flag information when the number of differences exceeds a reference number, enabling data migration before destruction occurs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is stored in floating gates to achieve nonvolatile storage, then data retention is improved, but electron leakage causes threshold value fluctuations leading to data deterioration
Solution Approach 1:
The patent performs preliminary reading of data at multiple voltage levels (actual read level and shifted higher level) before data destruction occurs. By comparing the readout data from both levels and counting differences, the system detects data retention status in advance and outputs flag information to enable preventive data migration, avoiding the harmful effect of electron leakage导致的 data deterioration.
2Measurement precision
If multiple read levels are used to detect data retention, then data deterioration detection is improved, but device complexity increases
Solution Approach 1:
The patent merges the data retention detection function with the existing readout circuit structure. The sense amplifier and data latch circuits are reused to perform both normal data reading and retention status detection. By combining these functions and using the same hardware resources for dual purposes, the patent achieves improved measurement precision without proportionally increasing device complexity.
Solution Approach 2:
The patent creates a copy of the data reading process by performing reads at both the actual read level and a shifted higher level. This copying approach allows comparison of readout data from different voltage levels to detect data retention, while using the same existing readout circuit hardware for both readings, thereby avoiding additional complex circuits.
3Reliability
If data migration is performed to prevent data destruction, then data reliability is improved, but loss of time occurs during migration process
Solution Approach 1:
The patent implements a feedback mechanism where the controller continuously monitors data retention status by comparing readout data from different voltage levels. When the number of differences exceeds a reference value, flag information is output to trigger data migration. This feedback loop enables timely detection and response, improving data reliability while minimizing the time loss by initiating migration only when necessary based on actual retention conditions.
Data Source
AI summary
A semiconductor memory device includes a memory cell array including a plurality of memory cells, a first data latch circuit, a second data latch circuit, an arithmetic circuit, a counter circuit, and a controller. And controller compares the number (N) counted by the counter circuit with a reference number (M), and performs control to output flag information outside if N≧M.