Non-volatile Memory Error Compensation via Reverse Reading
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Non-volatile memory devices face issues with correct programming due to source terminal noises caused by parasitic capacitance/parasitic resistances, leading to incomplete programming and reduced success rates in verification processes.
Innovation Solution
A non-volatile memory device and error compensation method that includes a memory block, word line driver, and bit line circuit, where a verification process is performed through reverse reading and application of a preset voltage to determine if memory cells are correctly programmed, with a second programming process executed for cells that are not, thereby reducing noise influence and improving programming success rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a first programming process is performed on memory cells, then programming speed is improved, but source terminal noises cause programming errors in some cells
Solution Approach 1:
The patent applies preliminary action by performing a first verification process immediately after the first programming process to identify cells that were not correctly programmed. This allows for early detection of programming errors caused by source terminal noises, enabling targeted re-programming of only the affected cells rather than re-programming the entire block, thus maintaining high productivity while ensuring programming accuracy.
Solution Approach 2:
The patent implements feedback through the verification process that reads back the programmed data from memory cells and compares it with the intended programming data. When discrepancies are detected, the system provides feedback by identifying the specific cells with errors and triggering a second programming process only for those cells, thereby ensuring high reliability without sacrificing overall programming efficiency.
2Reliability
If a verification process is performed on all memory cells, then programming accuracy is improved, but processing time increases
Solution Approach 1:
The patent applies local quality by differentiating the verification approach based on individual cell status. Instead of uniformly treating all memory cells, the system performs verification on all cells initially, then applies a second programming process only to the specific local region (individual cells or small groups) that were found to be incorrectly programmed. This localized re-programming approach significantly reduces the total time required compared to re-verifying or re-programming the entire memory block.
Solution Approach 2:
The patent segments the verification and re-programming process by identifying and isolating only the memory cells that require correction. The second programming process is applied segmentally to only those specific cells that failed the verification, rather than applying it to the entire memory block. This segmentation reduces the overall processing time while maintaining high programming accuracy.
3Reliability
If a second programming process is performed on specific memory cells, then programming accuracy is improved, but device complexity increases
Solution Approach 1:
The patent applies self-service by implementing an automatic error detection and correction mechanism. The verification process automatically identifies cells with programming errors, and the controller automatically triggers a second programming process for those specific cells without requiring external intervention or complex manual control. This self-service approach manages the increased complexity internally while maintaining a simple external interface.
Solution Approach 2:
The patent uses preliminary action by pre-identifying and marking the specific memory cells that require re-programming through the verification process. This preliminary identification simplifies the subsequent second programming process by providing a ready-made list of target cells, reducing the control complexity during the actual re-programming phase. The system prepares the correction plan in advance, making the execution phase more straightforward.
Data Source
AI summary
A non-volatile memory device and an error compensation method for verifying the same are provided. The non-volatile memory device includes a memory block, a word line driver, a bit line circuit and a controller. The memory block includes multiple memory cells. After a first programming process and a first verification process are performed on the memory cells, the controller performs reverse reading to the control terminals of the memory cells, applies a preset voltage to the control terminals of the memory cells according to preset programming data by using the word line driver, reads data from the memory cells by using the bit line circuit, and determines whether the data of each memory cell is normal according to the data read from the memory cells. When the data of specific memory cells is not normal, the controller performs a second programming process to the specific memory cells.