Moving Program Verify Levels for Flash Memory Programming
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Solution Overview
Problem
Conventional flash memory programming using a single program verify level can be inefficient, as faster memory elements receive unnecessary high voltage pulses, leading to overprogramming and reduced programming speed, reliability, and density.
Innovation Solution
Implementing a system that adjusts program verify levels during programming, applying multiple pulses with varying voltage levels and pulse widths to efficiently program memory elements to a target threshold, ensuring all elements reach the desired state without overprogramming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single program verify level is used during programming, then the programming process is simple, but faster memory elements receive unnecessary high voltage pulses leading to overprogramming and reduced reliability
Solution Approach 1:
The single program verify level is segmented into multiple program verify levels (first program verify level and second program verify level). This segmentation allows different voltage pulse conditions to be applied to different groups of memory elements, preventing overprogramming of faster elements while ensuring slower elements receive adequate programming pulses.
Solution Approach 2:
The programming system dynamically adjusts program verify levels and associated voltage pulse parameters (drain voltage, gate voltage, pulse width) based on the programming progress and characteristics of memory elements. This dynamic adaptation optimizes programming conditions for different memory element groups, improving reliability without excessive complexity.
2Device complexity
If a single program verify level is used, then the programming control is simple, but programming speed is reduced due to unnecessary pulses on fast elements
Solution Approach 1:
Memory elements are segmented into different groups (first group and second group) with different programming characteristics. Each group receives customized programming pulses with appropriate voltage levels and durations, allowing fast elements to be programmed efficiently without waiting for slower elements, thereby increasing overall programming speed.
Solution Approach 2:
Programming parameters (drain voltage, gate voltage, pulse width) are changed and optimized for different memory element groups. By adjusting these parameters dynamically, the system achieves faster programming speeds for fast elements while maintaining adequate programming for slower elements, improving overall productivity.
3Reliability
If high voltage pulses are applied to all memory elements, then all elements can be programmed, but faster elements become overprogrammed reducing density and reliability
Solution Approach 1:
Different voltage pulse conditions are applied to different groups of memory elements based on their individual programming characteristics. Faster memory elements receive lower voltage pulses or shorter duration pulses, while slower elements receive higher voltage pulses, achieving precise threshold voltage control and tight final distributions without overprogramming.
Solution Approach 2:
The system incorporates verification steps where memory elements are tested against program verify levels, and programming parameters are adjusted based on verification results. This feedback mechanism ensures that all elements reach the desired threshold voltage without overprogramming, improving both reliability and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances programming speed, tightens final distributions, improves reliability, increases data storage density, and extends the useful life of memory devices by optimizing programming conditions dynamically.
Implementation Method 1
Programming of selected memory elements, or portions thereof (e.g. a memory element of a memory cell that contains multiple memory elements) can be performed by applying a number of programming pulses (e.g., voltage pulses) to the selected memory elements until the selected memory elements are programmed to the desired threshold charge level
Data Source
AI summary
Systems, methods, and devices that employ moving program verify levels to facilitate programming data to memory elements in a memory component are presented. A program component can employs a specified number of program verify (PV) levels where a first program pulse is applied to a selected group of memory elements to facilitate verifying the cells to pass the first PV level. The PV level can be moved to a next PV level that is a higher charge level than or equal to the first PV level, and a subset of the group of cells that are below the next PV level are selected and a next program pulse is applied to the subset of cells to facilitate verifying the cells to pass the next PV level. The moving PV level process can continue until the group of memory elements is verified to pass the target PV level.