NOR Flash Memory Sense Amplifier Clock Synchronization
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Solution Overview
Problem
Conventional NOR flash memory devices experience sense operation failures due to asynchronous operation with respect to the clock signal, leading to potential data corruption from noise in the power supply or ground voltage.
Innovation Solution
A control circuit synchronizes the sense operation with a clock signal, generating a sense signal during noise-free periods to ensure accurate data sensing and outputting data while minimizing the impact of power supply or ground noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the sense amplifier performs sense operation asynchronously with the clock signal, then the sense operation can be completed, but sense operation failures occur due to noise from the output driver affecting the power supply voltage or ground voltage
Solution Approach 1:
The patent implements periodic action by synchronizing the sense operation with the clock signal. The control circuit generates a sense signal that is activated only during specific clock cycles when the output driver is not switching, creating a periodic window for safe sensing operations. This resolves the contradiction by establishing regular intervals where the harmful noise from the output driver does not interfere with the sense amplifier operation.
Solution Approach 2:
The patent applies preliminary action by having the control circuit预先 generate and provide the sense signal at the appropriate timing before the output driver generates noise. The sense operation is initiated in advance during clean power supply periods, ensuring that data sensing occurs before the harmful noise from output driver switching affects the power supply voltage or ground voltage.
2Object-affected harmful factors
If the sense operation is synchronized with the clock signal, then noise-related errors are reduced, but the timing control complexity increases
Solution Approach 1:
The control circuit performs multiple functions: it generates the sense signal, synchronizes it with the clock signal, and controls the timing coordination between the sense amplifier and output driver. By making the control circuit multi-functional, the patent reduces the need for additional separate control circuits, thereby limiting the increase in device complexity while achieving noise-related error reduction through synchronized operation.
3Device complexity
If the sense amplifier operates independently without clock synchronization, then the operation is simpler, but data corruption may occur from power supply noise
Solution Approach 1:
The control circuit acts as an intermediary between the clock signal and the sense amplifier. It receives the clock signal, processes it to generate appropriately timed sense signals, and provides these to the sense amplifier. This intermediary function maintains relative operational simplicity while preventing data corruption by ensuring the sense amplifier only operates during noise-free periods, thus protecting against power supply noise without requiring complex direct synchronization.
Data Source
AI summary
A NOR flash memory is disclosed including a memory cell, sense amplifier output driver, and control circuit. A sense period for a sense operation performed by the sense amplifier is made synchronous with a clock signal so as to avoid power supply or ground signal noise generated by operation of the output driver.