Semiconductor Memory Device Preventing Over-Stress via eFUSE Switch Control
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Solution Overview
Problem
Semiconductor memory devices face over-stress and performance changes due to repeated application of specific stress items during testing, leading to test failures and potential damage to memory chips.
Innovation Solution
A semiconductor memory device with a switch control part that isolates the power supply to the memory core after the first application of a specific stress item, preventing further over-stress by using an eFUSE circuit and PMOS transistors to manage power delivery based on the presence of the stress item.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the test device repeatedly applies specific stress items to memory chips during retesting, then test coverage and reliability are improved, but the memory cells undergo over-stress leading to performance changes and potential damage
Solution Approach 1:
The patent applies preliminary action by using an eFUSE circuit to record whether a specific stress item has been applied to each memory chip before retesting. The eFUSE is programmed during the first stress application, creating a permanent mark that prevents future stress application to the same chip. This preliminary recording action resolves the contradiction by enabling the test system to distinguish between chips that have already undergone stress testing and those that haven't, thereby preventing over-stress damage while maintaining test reliability.
Solution Approach 2:
The patent introduces an intermediary mechanism - the eFUSE circuit and switch control part - that mediates between the test device's desire to retest chips and the need to prevent over-stress. The eFUSE acts as an intermediary record-keeping element, while the switch control part acts as an intermediary gatekeeper that controls power supply to the memory core based on the eFUSE state. This intermediary system resolves the contradiction by automatically preventing stress application to chips that have already been tested, eliminating the need for manual tracking while protecting against over-stress.
2Measurement precision
If the test device applies high voltage stress items to test memory cell stability, then testing accuracy is improved, but the memory cells are exposed to harmful high voltage levels that can cause damage
Solution Approach 1:
The patent applies preliminary action by programming the eFUSE circuit before applying high voltage stress items. The eFUSE is configured in advance to record the fact that stress has been applied, creating a preventive mechanism that stops subsequent stress application. This preliminary recording enables accurate testing to be performed once, while preventing repeated exposure to harmful high voltage levels that would damage the memory cells.
Solution Approach 2:
The patent converts the potentially harmful effect of high voltage stress into a beneficial testing mechanism by using the eFUSE circuit to track and limit stress application. The high voltage stress, which could damage cells if applied repeatedly, is transformed into a controlled testing tool by the eFUSE's ability to record and prevent re-application. This converts the harmful repetitive stress into a beneficial one-time stress test that accurately evaluates memory cell stability without causing damage.
3Productivity
If the test device performs retesting on all memory chips after contact defects, then test completeness is improved, but chips that already received stress items are subjected to additional over-stress
Solution Approach 1:
The patent introduces an intermediary system consisting of the eFUSE circuit and switch control part that mediates between the need for complete retesting and the need to prevent repeated stress damage. The eFUSE circuit serves as an intermediary record-keeping mechanism that identifies which chips have already undergone stress testing, while the switch control part serves as an intermediary gatekeeper that prevents stress application to already-tested chips. This intermediary system enables complete retesting of all chips for contact defects while automatically protecting against repeated stress application.
Solution Approach 2:
The patent implements feedback by using the eFUSE circuit to provide information about previous stress application status back to the switch control part. When the test device attempts to apply stress items during retesting, the switch control part queries the eFUSE to determine whether the chip has already been stressed. This feedback mechanism enables the system to make informed decisions about whether to apply stress, thereby maintaining test completeness while preventing repeated stress damage to already-tested chips.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents over-stress and maintains normal operation by ensuring the specific stress item is applied only once, thereby mitigating damage and performance changes in memory cells during retesting.
Implementation Method 1
a switch control part that controls the switch part, wherein the memory core is tested for stability in response to the specific stress item, and the switch control part isolates the switch part if the specific stress item is supplied to the memory core two or more times
Implementation Method 2
using an eFUSE circuit and PMOS transistors to manage power delivery based on the presence of the stress item
Data Source
AI summary
A semiconductor memory device includes a memory core which receives a specific stress item and a pattern item from an external source, a switch part which provides the power supplied from an external source and a switch control part which controls the switch part. The memory core responds to the specific stress item to be tested for stability, and the switch control part isolates the switch part if the specific stress item is supplied to the memory core two or more times.