Nonvolatile Memory Erase Method With Adaptive Word Line Timing
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Solution Overview
Problem
Nonvolatile memory devices, such as flash memory, face performance degradation due to varying erase speeds across word lines, leading to wide threshold voltage distributions and inefficient erase operations.
Innovation Solution
An erase method that performs a first erase operation on memory cells connected to multiple word lines, determines the erase operation speed by applying a verify voltage, and adjusts the effective erasing time for each word line based on the error rate of memory cells, allowing for a second erase operation tailored to each region's needs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a uniform erase operation is applied to all word lines, then the erase process is simple to control, but the threshold voltage distribution becomes wide due to varying erase speeds across word lines
Solution Approach 1:
The patent segments the erase operation into multiple erase periods with different erase times for different word lines. Instead of applying a uniform erase time to all word lines, the method divides the erase process into first and second erase periods, where the second erase period applies extended erase times to specific word lines based on their individual erase speeds, thereby narrowing the threshold voltage distribution while maintaining manageable control complexity.
Solution Approach 2:
The patent implements dynamic adjustment of erase times for different word lines based on measured erase speeds. The erase control logic dynamically determines the number of second erase periods for each word line according to its specific erase characteristics, transforming the static uniform erase approach into a dynamic adaptive process that optimizes erase precision for each word line.
2Reliability
If the erase time is extended for all word lines to ensure complete erasure, then erase reliability improves, but erase speed and productivity decrease
Solution Approach 1:
The patent applies partial extended erase action only to word lines that require it, rather than extending the erase time for all word lines. By identifying specific word lines with slower erase speeds and applying additional second erase periods only to those word lines, the method ensures complete erasure where needed while maintaining fast erase speeds for word lines that already erase completely within the first erase period.
Solution Approach 2:
The patent implements local quality by applying different erase strategies to different word lines based on their individual characteristics. Fast-erasing word lines receive only the standard first erase period treatment, while slow-erasing word lines receive additional second erase periods, optimizing both reliability and productivity by matching erase effort to actual need.
3Manufacturing precision
If a verify operation is performed to determine erase speed for each word line, then erase precision improves, but operation time and complexity increase
Solution Approach 1:
The patent performs preliminary verify operations during the first erase period to measure erase speeds of different word lines before executing the second erase period. By conducting these verification measurements in advance, the system gathers necessary information about word line characteristics early, enabling optimized erase time allocation in the second erase period without adding significant overall time penalty.
Solution Approach 2:
The patent maintains continuity of useful action by integrating the verify operation into the erase process itself rather than as a separate standalone step. The verification of erase speeds occurs continuously during the first erase period while erasure is being performed, and the results are immediately utilized to configure the second erase period, eliminating idle time and maintaining productive action throughout.
Data Source
AI summary
A method of erasing a memory device, the method of erasing the memory device including: performing, in a first erase period, a first erase operation on memory cells respectively connected to a plurality of word lines, wherein at least one of the memory cells, which is included in a memory block, is not erase-passed; determining, after the first erase period, an erase operation speed by applying a verify voltage to at least one of the plurality of word lines, and determining an effective erasing time for each word line based on the determined erase operation speed; and performing, in a second erase period, a second erase operation on the memory cells respectively connected to the plurality of word lines based on the determined effective erasing times.