Non-Volatile Memory Operation Method for Second-Bit Effect Reduction
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Solution Overview
Problem
Non-volatile memory devices, particularly nitride read-only memory (NROM) cells, face challenges with the second-bit effect, where the state of one bit affects the reading of another, leading to increased threshold voltage and potential misjudgment during reading operations, especially in multi-level memory cells, reducing reliability and operation window.
Innovation Solution
An operation method for non-volatile memory that employs two sets of programming verification levels and reading levels, where the level of the second storage position determines the operation levels for the first storage position, allowing for accurate state judgment by adjusting the programming and reading levels based on the relative levels of the storage positions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If reverse read scheme is used to read one bit of the memory cell, then the reading operation can be performed, but the second bit effect causes threshold voltage drift and narrows the operation window
Solution Approach 1:
The patent applies parameter changes by adjusting the read voltage level based on the state of the second bit. When the second bit is in state '0' (higher threshold voltage), a lower read voltage is used; when the second bit is in state '1' (lower threshold voltage), a higher read voltage is used. This dynamic adjustment of the read voltage parameter compensates for the threshold voltage drift caused by the second bit effect, maintaining accurate reading operations while preserving the operation window.
2Quantity of substance
If multi-level memory cell is used to increase storage capacity, then more data can be stored, but the second bit effect becomes more severe and complicates the operation
Solution Approach 1:
The patent applies segmentation by dividing the reading operation into two independent stages: first reading the second bit to determine its state, then using that information to select the appropriate read voltage for reading the first bit. This segmentation of the reading process into conditional stages simplifies the overall operation of multi-level memory cells by breaking down the complex interaction between bits into manageable, sequential steps, thereby reducing operation complexity while maintaining high storage capacity.
3Ease of operation
If conventional read voltage is used regardless of second bit state, then operation is simple, but misjudgment occurs due to threshold voltage drift
Solution Approach 1:
The patent implements feedback by using the read result of the second bit to dynamically adjust the read voltage applied to the first bit. The system reads the second bit first, uses its state (0 or 1) as feedback information, and then selects the appropriate read voltage level for accurately reading the first bit. This feedback mechanism ensures high judgment accuracy while maintaining operational simplicity, as the voltage adjustment is automatically determined by the second bit's state without requiring complex external control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method effectively reduces the second-bit effect by increasing the operation window and preventing misjudgments in multi-level memory cells, ensuring accurate data reading and programming by using distinct sets of levels for higher and lower level storage positions.
Implementation Method 1
the silicon nitride material is characteristic of trapping charges (electrons) when the Nbit memory cell is programmed
Data Source
AI summary
An operation method of a non-volatile memory for reducing the second-bit effect in the non-volatile memory is suitable for an N-level memory cell having a first storage position and a second storage position (wherein N is a positive integer greater than 2). The method includes following steps: determining sets of operation levels for operating the first storage position according to the level of the second storage position; when the level of the second storage position is a lower level, operating the first storage position according to a first set of operation levels; when the level of the second storage position is a higher level, operating the first storage position according to a second set of operation levels. Each of the levels in the second set of operation levels is greater than the corresponding level in the first set of operation levels.