Nonvolatile Memory Refresh via Threshold Voltage Comparison
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Solution Overview
Problem
Conventional flash memory experiences inefficiencies in refreshing non-selected blocks during erasure, leading to erroneous data and prolonged operation times due to disturbances in threshold voltages and limited programming frequencies, which result in poorer data storage characteristics and increased time for achieving desired threshold voltages.
Innovation Solution
A non-volatile memory apparatus with a control circuit that determines whether memory cells in non-selected blocks need refreshing by comparing their threshold voltages to refresh read and program verify reference voltages, allowing for selective and batch refreshing to prevent unnecessary operations and maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a moderate reverse bias voltage is applied to a non-selected portion of the physical block to partially erase it, then the erasure operation can be performed, but the threshold voltages of memory cells in non-selected blocks are disturbed causing erroneous data
Solution Approach 1:
The physical block is divided into multiple memory sectors, and the refresh operation is segmented to only affect non-selected blocks that require refreshing. This segmentation allows the erasure operation to proceed while isolating and refreshing only the specific memory sectors that experienced threshold voltage disturbance, rather than refreshing the entire block.
Solution Approach 2:
The control circuit monitors threshold voltages of memory cells and identifies those that fall within a specific range indicating disturbance. Based on this feedback, the control circuit selectively refreshes only the affected memory cells in non-selected blocks, adjusting the refresh operation dynamically according to the actual state of memory cells.
2Reliability
If memory cells are refreshed one by one to ensure data correctness, then data integrity is maintained, but the refreshing time increases significantly
Solution Approach 1:
Multiple memory cells that require refreshing are merged into a single batch operation. The control circuit identifies all memory cells in non-selected blocks whose threshold voltages fall within the disturbance range and refreshes them simultaneously in one operation, rather than processing them individually, thereby maintaining data integrity while significantly reducing refresh time.
Solution Approach 2:
The control circuit performs preliminary identification of memory cells requiring refresh before executing the refresh operation. By pre-screening memory cells based on their threshold voltage ranges and preparing a refresh list in advance, the system can execute a coordinated batch refresh operation without the overhead of sequential individual refresh operations.
3Reliability
If memory cells with lower threshold voltages are refreshed, then data storage characteristics may be improved, but the driving voltage of bit lines becomes insufficient causing operational problems
Solution Approach 1:
The control circuit changes the operating parameters by identifying and refreshing only memory cells whose threshold voltages fall within a specific range that indicates disturbance without being excessively low. This parameter-based selection ensures that refreshed cells have adequate threshold voltages to maintain proper bit line driving capability while still correcting disturbed data.
Solution Approach 2:
Different refresh strategies are applied to different memory cells based on their local threshold voltage characteristics. Memory cells with threshold voltages in the disturbance range are refreshed, while those with excessively low threshold voltages are excluded from refresh operations to preserve sufficient driving voltage for bit lines.
4Reliability
If flash memory is erased and programmed frequently to maintain data correctness, then data integrity can be maintained, but the memory grows older and programming/erasing time increases
Solution Approach 1:
Instead of performing full block erasure and re-programming to ensure data correctness, the system applies partial action by refreshing only the specific memory cells in non-selected blocks that show signs of disturbance. This partial refresh approach maintains data integrity while avoiding the wear and time associated with complete erase-program cycles.
Solution Approach 2:
The threshold voltage disturbance caused by erasure operations on selected blocks is converted into a benefit by using it as an indicator to trigger selective refresh operations on non-selected blocks. This transforms the harmful side effect of threshold voltage disturbance into a mechanism for maintaining data correctness without requiring full erase-program cycles.
Data Source
AI summary
A non-volatile memory apparatus and a refresh method thereof are provided. A control circuit determines whether threshold voltages of memory cells in a memory sectors are larger than a refresh read reference voltage and smaller than a refresh program verify reference voltage, and the control circuit determines that a memory cell needs refreshing if the threshold voltage of the memory cell is larger than the refresh read reference voltage and smaller than the refresh program verify reference voltage.