Reference Voltage Generator Circuit for Non-Volatile Memory
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Solution Overview
Problem
Existing generator circuits for reference voltage in memory devices with non-volatile cells, such as EEPROM, face challenges in efficiently reducing the physical dimensions of memory cells while ensuring accurate erasing and programming, often requiring excessive ultraviolet exposure for reference cells, leading to increased complexity and cost, and occupying excessive silicon area due to large filter capacitors.
Innovation Solution
A voltage generator circuit that uses reference cells with accessible floating gate regions, periodically discharged through a biasing block, comprising a converter, comparator, and biasing block to generate a reference voltage without ultraviolet rays, allowing for compact and efficient biasing of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If reference cells are used to generate reference voltage in memory devices with reduced dimensions, then the memory cell size is reduced, but excessive ultraviolet exposure is required for erasing reference cells
Solution Approach 1:
The invention changes the erasing mechanism from ultraviolet exposure to electrical field application. By applying a high voltage pulse to the control gate of reference cells, charges are electrically removed from the floating gate, eliminating the need for UV exposure and significantly reducing erasing time
Solution Approach 2:
The invention replaces the optical system (ultraviolet light source and lens) with an electrical system (voltage pulse generator). This substitution eliminates the need for UV exposure while achieving the same erasing function through electrical field effects on the floating gate charges
2Stability of the object's composition
If large filter capacitors are used in the voltage generator circuit, then stable reference voltage is achieved, but excessive silicon area is occupied
Solution Approach 1:
The invention changes the capacitance value parameter to a much smaller range (few femtofarads) by implementing a distributed capacitance structure across multiple reference cells rather than using a single large capacitor, thereby reducing silicon area while maintaining voltage stability
Solution Approach 2:
The invention segments the filtering function across multiple reference cells, where each cell contributes a small parasitic capacitance. The cumulative effect of these distributed small capacitances provides the necessary voltage stability without requiring a single large capacitor that would occupy excessive silicon area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables efficient and compact generation of a reference voltage, reducing occupied area and erasing time, while ensuring accurate biasing of memory cells independently of their physical dimensions, without the need for ultraviolet exposure.
Implementation Method 1
a first biasing block, controlled by a first initialization signal, suitable for periodically discharging, by biasing a fourth terminal (floating gate contact terminal) at a predetermined biasing voltage, possible charges contained in the floating gate region of the reference cell
Data Source
AI summary
A generator circuit generates a reference voltage on an output terminal connected to a matrix of non-volatile memory cells and includes a comparator positioned between a common node and the output terminal. The comparator has first and second input terminals and an output terminal suitable for supplying a compared voltage given by comparing first and second voltage values present on the first and second input terminals. The circuit includes a reference cell inserted between the common node and a first voltage reference. Advantageously, the reference cell comprises a floating gate with a contact terminal coupled to a biasing block, having an input terminal connected to the output terminal of the generator circuit and being suitable for periodically biasing the floating gate contact terminal at a biasing voltage of a second voltage reference.