3D NAND Memory String Erasure via Selective Bit Line Voltage
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Solution Overview
Problem
The existing 3D NAND flash memory erasing method, which operates in units of memory blocks, faces challenges with increasing memory cell density, leading to slowed erasing speed, prolonged erasing time, and potential data loss due to frequent block erasure.
Innovation Solution
A control method for a memory that applies a bit line erasing voltage to a select bit line, a top select gate voltage to form a potential difference with the bit line, and a word line erasing voltage lower than the bit line erasing voltage to corresponding word lines, allowing for selective erasure of memory strings without the need for data migration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data migration is performed before block erasure, then data retention is maintained, but erasing time is prolonged
Solution Approach 1:
The patent divides the memory block into multiple memory strings and performs erasure on a per-string basis rather than erasing the entire block. This segmentation allows selective erasure of only those strings containing invalid data, eliminating the need to migrate data from all strings and significantly reducing erasure time while maintaining data retention for valid strings.
Solution Approach 2:
The patent applies different voltage conditions to different memory strings based on their individual data states. By identifying strings with invalid data and applying erasure voltage only to those specific strings, the system achieves localised erasure that maintains overall data retention while reducing total erasure time.
2Reliability
If entire block erasure is performed, then data retention is maintained, but memory cell degradation increases
Solution Approach 1:
The patent segments the erasure operation to affect only individual memory strings rather than the entire block. This allows valid memory cells in other strings to remain unaffected, reducing cumulative degradation from frequent erasure operations while maintaining data retention through selective erasure of only invalid strings.
Solution Approach 2:
The patent applies erasure voltage locally to specific memory strings that contain invalid data, rather than applying it uniformly across the entire block. This localized approach minimizes the number of erasure cycles experienced by valid memory cells, thereby reducing degradation while preserving data retention.
3Quantity of substance
If memory density increases, then storage capacity improves, but erasing speed decreases
Solution Approach 1:
The patent divides the high-density memory block into multiple independent memory strings that can be processed individually. This segmentation enables parallel or selective erasure of only the necessary strings, maintaining high erasing speed even as overall memory capacity increases through higher cell density.
Solution Approach 2:
The patent performs partial erasure by targeting only the specific memory strings that require erasure rather than erasing the entire block. This partial action approach maintains erasing speed by avoiding unnecessary erasure operations on valid data, even as memory capacity grows with increased density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method significantly improves erasing speed and reduces erasing time by eliminating the need for data migration, thereby enhancing memory performance and data retention.
Implementation Method 1
applying a top select gate voltage to a top select gate to form a potential difference between the top select gate and the select bit line
Data Source
AI summary
The embodiments of the disclosure provide a control method and apparatus for a memory, and a storage medium. The memory has memory blocks, and each memory block has memory strings. Each of the memory strings includes a channel layer with an N-type doped top region. In a memory block, a bit line erasing voltage is applied to a select bit line, and an erasing prohibition voltage is applied to an unselect bit line. A top select gate voltage lower than the bit line erasing voltage is applied to a top select gate. When a word line erasing voltage lower than the bit line erasing voltage is applied to the corresponding word line connected to a memory string corresponding to the select bit line and the unselect bit line, the memory string corresponding to the select bit line is erased.