Semiconductor Memory Device Bit Line Voltage Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional flash memory devices face challenges in forming a narrow threshold voltage distribution during programming, as they apply the same program voltage to all memory cells connected to a word line, making it difficult to achieve precise control over the programming state.
Innovation Solution
A semiconductor memory device and method that dynamically adjust the bit line voltage based on the threshold voltage of a selected memory cell, using a peripheral circuit to apply varying bit line voltages when the threshold voltage is between first and second verification voltages, and calculating a second bit line voltage based on the threshold voltage to optimize programming pulses and achieve a narrow threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the same program voltage is applied to all memory cells connected to the same word line, then the programming operation can be performed uniformly across all cells, but it becomes difficult to achieve precise control over the programming state and form a narrow threshold voltage distribution
Solution Approach 1:
The patent applies different bit line voltages to different memory cells based on their individual threshold voltage characteristics. Specifically, when a memory cell's threshold voltage is between first and second verification voltages, a first bit line voltage is applied; when it exceeds the second verification voltage, a second bit line voltage is applied. This local differentiation enables precise control over the programming state of each memory cell, achieving a narrow threshold voltage distribution while managing complexity through targeted voltage application.
Solution Approach 2:
The patent dynamically adjusts the bit line voltage based on the real-time threshold voltage status of each memory cell. The programming process transitions from applying a first bit line voltage during intermediate states to applying a second bit line voltage when the threshold voltage exceeds the second verification voltage. This dynamic voltage adjustment enables precise control over the programming process, allowing the system to achieve narrow threshold voltage distribution adaptively.
2Manufacturing precision
If a constant bit line voltage is applied regardless of threshold voltage, then the programming process is simple to implement, but the threshold voltage distribution becomes wide and programming precision is poor
Solution Approach 1:
The patent implements a feedback mechanism where the bit line voltage is adjusted based on the threshold voltage verification results of each memory cell. The system continuously monitors whether the threshold voltage exceeds the second verification voltage and accordingly switches between the first and second bit line voltages. This feedback-driven approach significantly improves programming precision and narrows the threshold voltage distribution, while the automated feedback loop manages operational complexity.
Solution Approach 2:
The patent changes the bit line voltage parameter dynamically during the programming process. When the memory cell's threshold voltage is between the first and second verification voltages, a first bit line voltage is applied; when it exceeds the second verification voltage, a second bit line voltage is applied. This parameter change strategy enables precise control over the programming state, achieving narrow threshold voltage distribution while managing complexity through systematic voltage transitions.
Data Source
AI summary
The present disclosure relates to a semiconductor device and a method of operating the semiconductor device, and particularly to a semiconductor memory device including a memory cell array and a method of operating the semiconductor memory device. The memory device includes a memory cell array including a plurality of memory cells; and a peripheral circuit configured to program a selected memory cell into a target program state, wherein the peripheral circuit performs a program operation by applying a bit line voltage determined according to the threshold voltage to a bit line of the selected memory cell when a threshold voltage of the selected memory cell is higher than a first verification voltage and is lower than a second verification voltage.