Row Selector Using Medium Voltage Transistors for Flash Memory
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Solution Overview
Problem
Existing non-volatile memory devices require high voltage transistors for row selectors, which increase chip area and manufacturing complexity due to the need for different oxide thicknesses and additional manufacturing steps.
Innovation Solution
Implementing a row selector using medium voltage transistors that can sustain voltage differences up to half the maximum voltage of high voltage transistors, reducing the need for high voltage transistors and simplifying the manufacturing process by using a single oxide thickness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high voltage transistors are used for row selectors, then the ability to handle required voltages during programming and erasing is improved, but chip area and manufacturing complexity increase
Solution Approach 1:
The patent changes the voltage parameter by introducing medium voltage transistors with threshold voltages between 0.7V and 1.2V, which is higher than standard low voltage transistors (0.4V-0.6V) but lower than high voltage transistors. This intermediate voltage parameter allows the row decoder to handle the 0.9V-1.8V supply voltage range without requiring high voltage transistors, thereby reducing chip area while maintaining adequate voltage handling capability for flash memory operations.
2Reliability
If high voltage transistors are used for row selectors, then the ability to handle required voltages during programming and erasing is improved, but manufacturing complexity increases due to different oxide thicknesses and additional manufacturing steps
Solution Approach 1:
The patent changes the voltage parameter by introducing medium voltage transistors with threshold voltages between 0.7V and 1.2V, which is higher than standard low voltage transistors (0.4V-0.6V) but lower than high voltage transistors. This intermediate voltage parameter allows the row decoder to handle the 0.9V-1.8V supply voltage range without requiring high voltage transistors, thereby reducing chip area while maintaining adequate voltage handling capability for flash memory operations.
3Ease of manufacture
If medium voltage transistors are used instead of high voltage transistors, then chip area and manufacturing complexity are reduced, but voltage handling capability may be compromised
Solution Approach 1:
The patent changes the voltage parameter by introducing medium voltage transistors with threshold voltages between 0.7V and 1.2V, which is higher than standard low voltage transistors (0.4V-0.6V) but lower than high voltage transistors. This intermediate voltage parameter allows the row decoder to handle the 0.9V-1.8V supply voltage range without requiring high voltage transistors, thereby reducing chip area while maintaining adequate voltage handling capability for flash memory operations.
Data Source
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AI summary
A non-volatile memory device is provided. The memory device includes a memory matrix (105; 605) comprising a plurality of memory cells (Mc), arranged according to a plurality of rows and a plurality of columns. The memory device further includes a plurality of word lines (WL(i)); each word line is associated with one respective row of said plurality and is connected to the memory cells of the row; the word lines are grouped into at least one packet (WLP). The memory device includes a row selector (160; 660) coupled to the word lines and adapted to selectively biasing them. The row selector includes, for each packet of word lines, a plurality of first paths, wherein each first path is adapted to apply a first biasing voltage to a corresponding word line of the packet depending on an operation to be performed on the memory cells connected to the corresponding word line. Each first path includes at least a first (N(i)) and a second (P(i)) selection transistors series-connected between a first terminal and a second terminal of the first path. The second terminal is coupled to the corresponding word line. The memory device further includes enabling means (110) for commonly providing an enabling voltage to the first terminal of the first paths associated to a selected packet of word lines including a selected word line. The enabling voltage depends on the operation to be performed on the memory cells connected to the selected word line and is adapted to enable the execution of said operation. The memory device further includes selection means (150) for selecting one among said plurality of first paths. the selected first path corresponding to the selected word line. The selection means are adapted to activate the first selection transistor of the selected first path in order to obtain the first biasing voltage from the enabling voltage by a voltage drop introduced by the first selection transistor; said selection means are further adapted to activate the second selection transistor of the selected first path in order to transfer the first biasing voltage provided by the first selection transistor onto the selected word line.