Split Substrate Select Gates for Hierarchical Bitline Erase Control
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Solution Overview
Problem
Existing flash memory devices face inefficiencies in cost, performance, and power consumption due to their erase schemes, which involve repeatedly charging and discharging large wells, leading to increased chip size and cost.
Innovation Solution
A non-volatile memory device with at least two groups of NAND cell strings, each formed in separate pocket wells, where select devices electrically isolate local bitlines from global bitlines during erase operations, preventing unnecessary voltage distribution and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large wells are used to fabricate memory cells in flash memory devices, then the memory cells can be fabricated with sufficient electrical isolation, but the charge pumps needed to charge and discharge these wells occupy large chip area and increase chip size and cost
Solution Approach 1:
The patent divides the memory array into multiple independently erasable groups, each with its own select device and local bitlines. This segmentation allows erase operations to be performed on selected groups only, preventing unnecessary voltage distribution to unselected groups and reducing the load on charge pumps, thereby reducing chip area while maintaining electrical isolation
Solution Approach 2:
The patent introduces dynamic control through select devices that can electrically isolate local bitlines from global bitlines during erase operations. This dynamic isolation capability allows the system to adaptively control voltage distribution, enabling faster erase operations on selected groups without affecting unselected groups, thus reducing power consumption and charge pump requirements
2Productivity
If all local bitlines are connected to the global bitline during erase operations, then the erase operation can be performed, but unnecessary voltage is distributed to unselected memory blocks causing increased power consumption and slower erase speed
Solution Approach 1:
The select devices provide dynamic electrical isolation between local bitlines and global bitlines during erase operations. By controlling the select devices to isolate unselected local bitlines, the system dynamically prevents unnecessary voltage distribution, enabling faster erase operations on selected groups while reducing power consumption
Solution Approach 2:
The patent extracts unselected memory groups from the voltage distribution network during erase operations by using select devices to isolate their local bitlines from global bitlines. This extraction prevents these groups from consuming power during erase operations on selected groups, thereby reducing overall power consumption and improving erase speed
Data Source
AI summary
Generally, the present disclosure provides a non-volatile memory device having a hierarchical bitline structure for preventing erase voltages applied to one group of memory cells of the memory array from leaking to other groups in which erasure is not required. Local bitlines are coupled to the memory cells of each group of memory cells. Each local bitline can be selectively connected to a global bitline during read operations for the selected group, and all the local bitlines can be disconnected from the global bitline during an erase operation when a specific group is selected for erasure. Select devices for electrically connecting each bitline of a specific group of memory cells to the global bitline have device bodies that are electrically isolated from the bodies of those memory cells.