Memory Defective Address Processing Circuit for Repair Conflict Resolution

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Solution Overview

Problem

Existing memory devices face challenges in efficiently managing defective addresses and their corresponding redundant addresses, leading to repair conflicts and errors in data access.

Innovation Solution

A memory device is designed with a defective address information processing circuit that compares initial target defective address information with initial non-target defective address information, determines whether to process the non-target information based on the comparison, and outputs valid defective address information, thereby ensuring each defective address corresponds to only one redundant address.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If multiple pieces of initial defective address information are stored without comparison, then the storage capacity is increased, but repair conflicts occur and data access accuracy deteriorates

Engineering Contradiction:

Improvestorage capacityVSAvoiddata access accuracy

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent performs preliminary comparison between initial target defective address information and initial non-target defective address information before storing the data. This preliminary action identifies and eliminates duplicate defective addresses, ensuring that only unique defective address information is stored in the second defective address information memory, thereby preventing repair conflicts while maintaining storage capacity

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent introduces a defective address information processing circuit as an intermediary between the first defective address information memory and the second defective address information memory. This intermediary circuit compares the defective address information, determines validity, and filters out duplicates before storage, resolving the contradiction between storing more information and maintaining data accuracy

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If initial non-target defective address information is processed without comparison, then the processing speed is increased, but repair conflicts occur

Engineering Contradiction:

Improveprocessing speedVSAvoidrepair conflict avoidance

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The patent performs preliminary comparison of defective address information before processing and storage. By comparing initial target defective address information with initial non-target defective address information in advance, the system identifies duplicates and eliminates them before the actual processing occurs, preventing repair conflicts while maintaining efficient processing speed

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The defective address information processing circuit provides feedback by comparing the defective address information and determining whether to process the initial non-target defective address information based on the comparison result. This feedback mechanism ensures that only valid, non-duplicate information is processed and stored, preventing repair conflicts

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS20250174296A1Memory devices, operating methods thereof, memory systems

Publication Date: 2025.05.29 YANGTZE MEMORY TECH CO LTD

AI summary

A memory device includes a first defective address information memory configured to store multiple pieces of initial defective address information, the multiple pieces of initial defective address information include initial target defective address information and multiple pieces of initial non-target defective address information; a defective address information processing circuit connected to the first defective address information memory and configured to compare the initial target defective address information with each of the multiple pieces of initial non-target defective address information, determine whether to process the initial non-target defective address information based on a comparison result, and output multiple pieces of defective address information corresponding to the multiple pieces of the initial defective address information; and a second defective address information memory connected to the defective address information processing circuit and configured to store the multiple pieces of defective address information.