Semiconductor Memory Device N-well Merging for Area Reduction
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Solution Overview
Problem
Conventional semiconductor memory devices with horizontal cell and hierarchical bit line structures face challenges in reducing the area occupied by memory cells while maintaining processing accuracy and yield, due to the need for N-well isolation regions and separate substrate contacts.
Innovation Solution
A semiconductor memory device with a hierarchical bit line structure where the N-well region for memory cells and amplification circuit P-channel transistors are formed continuously, eliminating the need for isolation portions and allowing common use of substrate contacts, thereby reducing the bit line length and area occupancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If N-well regions for memory cells and amplification circuit are formed in isolated relation with N-well isolation portions, then processing accuracy and yield are maintained, but the area occupied by the memory device increases
Solution Approach 1:
The patent merges the N-well regions for memory cells and amplification circuit into a single continuous N-well region, eliminating the need for N-well isolation portions. This consolidation reduces the total area occupied by the memory device while maintaining proper electrical isolation through alternative means such as P-well regions and substrate contacts.
Solution Approach 2:
The continuous N-well region serves multiple functions simultaneously: it provides the N-well structure for both memory cell P-channel transistors and amplification circuit P-channel transistors, eliminates the need for separate isolation portions, and allows for optimized substrate contact placement. This multi-functionality reduces overall device area while maintaining processing accuracy.
2Reliability
If N-well isolation portions are provided to isolate N-well regions, then electrical isolation is achieved, but the bit line length and area occupancy increase
Solution Approach 1:
By merging the N-well regions into a continuous structure, the patent eliminates N-well isolation portions that would otherwise increase bit line length and area occupancy. Electrical isolation is maintained through the P-well regions and substrate contact configuration rather than through N-well isolation portions.
3Manufacturing precision
If separate substrate contacts are provided for memory cells and amplification circuit, then proper potential control is achieved, but the area occupied by the memory device increases
Solution Approach 1:
The patent implements a universal substrate contact structure that serves both the memory cells and the amplification circuit. This shared substrate contact configuration maintains proper potential control for both circuit blocks while reducing the total area occupied by the memory device compared to having separate substrate contacts.
Data Source
AI summary
A semiconductor memory device having a hierarchical bit line structure includes memory cells and an amplification circuit for amplifying a signal read from one of the memory cells via a bit line. A cell N-well region in which the P-channel transistors of the memory cell are formed and an amplification-circuit N-well region in which the P-channel transistors of the amplification circuit are formed are formed continuously.