Memory Device CA Training via Parity Error Feedback
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Solution Overview
Problem
Existing memory systems face challenges in accurately transmitting signals between a memory controller and a memory device due to large delay variations in the clock path, leading to parity errors and failures in CA signal capture.
Innovation Solution
The proposed memory system includes a clock distribution network that generates division clock signals for sampling command and data signals, a CA sampler for sampling the CA signal, a CA parity check circuitry for detecting parity errors, and a memory controller that enters CA training upon receiving a parity error signal, enabling the replica circuit for training without specific commands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock signal is transmitted from memory controller to memory device, then synchronization is achieved, but large delay variations occur in the clock path
Solution Approach 1:
The patent introduces a data clock signal as an intermediary carrier that conveys both clock timing and command/address data together through the same physical channel. This mediator approach eliminates separate clock path delays and achieves synchronized sampling without requiring precise separate clock timing, resolving the contradiction between reliable signal transmission and clock timing accuracy.
Solution Approach 2:
The patent merges the clock signal function and data signal function into a single data clock signal that serves dual purposes: providing timing reference and carrying command/address information. By combining these functions, the system eliminates the separate clock path that causes delay variations, achieving both reliable transmission and timing accuracy simultaneously.
2Productivity
If CA signal is sampled using division clock signal, then sampling is achieved, but parity errors occur due to timing misalignment
Solution Approach 1:
The patent implements a feedback mechanism where the memory device monitors incoming data clock signals for timing alignment and generates parity error signals when misalignment is detected. This feedback triggers CA training sequences that adjust timing parameters, creating a closed-loop system that maintains high sampling speed while ensuring capture accuracy through continuous timing validation and correction.
3Adaptability or versatility
If separate clock paths are used for CA and DQ signals, then independent timing control is achieved, but delay variations increase
Solution Approach 1:
The patent creates a universal data clock signal that serves multiple functions: it provides timing for CA signal sampling, timing for DQ signal sampling, and carries command/address data. This single multi-functional clock path eliminates timing inconsistencies between separate paths while maintaining the flexibility needed for independent timing control through selective sampling edges and training sequences.
Data Source
AI summary
Provided is a memory system including: a memory device; and a memory controller configured to transmit a command and address (CA) signal and a data clock (WCK) signal to the memory device, and transmitting a data (DQ) signal to the memory device or receive the DQ signal from the memory device. The memory device may include a clock distribution network configured to generate a first division clock signal for sampling the CA signal and a second division clock signal for sampling the DQ signal from the data clock signal, a CA sampler configured to sample the CA signal based on the first division clock signal, and a CA parity check circuitry configured to output a parity error signal in response to a parity error occurring for the CA signal, and the memory controller may include processing circuitry configured to enter CA training in response to receiving the parity error signal.