Precharge Timing Control for Semiconductor Memory Peak Current Reduction
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Solution Overview
Problem
In semiconductor memory devices, sharing elements between memory arrays increases impedance, leading to longer rise times for memory lines during write operations, particularly for high charge values, which affects data writing efficiency and increases peak current during precharge operations.
Innovation Solution
Incorporating precharge circuits that precharge memory lines to appropriate voltages prior to writing information and activating them at different timings to reduce peak current and equalize the time difference in writing between high and low charge values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data lines are precharged simultaneously during memory initialization, then the time to set data lines to high or low voltage is reduced, but an extreme amount of peak current is generated
Solution Approach 1:
The precharge operation is divided into multiple phases with different priorities. High-priority data lines are precharged first, followed by low-priority data lines after a delay. This segmentation of the precharge timing reduces simultaneous current draw while ensuring all lines are eventually precharged to the required voltage levels.
Solution Approach 2:
The precharge operation is performed in advance before actual memory write operations begin. By precharging data lines to the required voltage levels beforehand, the system eliminates the need for high current during write operations, thereby reducing peak current while maintaining fast write performance.
2Area of stationary object
If elements are shared between memory arrays, then chip size is reduced, but impedance increases and rise time for memory lines increases
Solution Approach 1:
Data lines are precharged to the required voltage levels before write operations begin. This preliminary action compensates for the increased impedance caused by shared elements, ensuring that when write operations occur, the lines are already at the correct voltage and can transition quickly despite the higher impedance.
Solution Approach 2:
The system changes the voltage parameter of data lines through precharge operations. By adjusting the voltage state of shared data lines before use, the system optimizes performance despite the impedance increases inherent in sharing elements between multiple memory arrays.
Data Source
AI summary
Apparatuses for controlling precharge timings in a semiconductor device are described. An example apparatus includes first and second memory and a precharge timing circuit. The first memory includes a first memory bank including a first data line and a second memory bank including a second data line. The second memory includes a third memory bank including a third data line and a fourth memory bank memory bank including a fourth data line. The precharge timing circuit provides first, second, third and fourth precharge activation signals. The first, second, third and fourth precharge activation signals activate precharge of the first, second, third and fourth data lines, respectively. The precharge timing circuit provides the first and second precharge activation signals at different times from each other. The precharge timing circuit provides the third and fourth precharge activation signals at different times from each other.