Dedicated Routing Interconnects for Programmable Logic Devices
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Solution Overview
Problem
The increasing complexity of programmable logic devices (PLDs) requires significant silicon area for interconnection resources to route signals to and from function-specific blocks (FSBs), often exceeding the area needed for the FSB's logic functionality, necessitating a more efficient use of interconnection resources to enhance FSB functionality without increasing silicon costs.
Innovation Solution
The implementation of dedicated routing interconnects from neighboring logic groupings to FSBs allows for expanded functionality while conserving interconnection resources, enabling additional independent inputs and operations without increasing the silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If traditional general interconnection resources are used to route signals to and from FSBs, then FSB functionality can be implemented, but the silicon area consumed by interconnection resources becomes significantly large, often exceeding the area needed for the FSB's logic functionality
Solution Approach 1:
The patent divides interconnection resources into two segments: general interconnection resources for standard routing, and dedicated routing interconnects specifically for FSB inputs. This segmentation allows each type of interconnect to be optimized for its specific purpose, reducing the overall silicon area required while maintaining full FSB functionality.
Solution Approach 2:
The patent implements dedicated routing interconnects that are locally optimized for FSB input requirements. These dedicated interconnects are positioned and configured specifically to serve FSBs, providing high-quality, low-area routing paths tailored to the specific needs of FSB signal inputs, rather than using generic interconnection resources for all routing needs.
2Adaptability or versatility
If FSB output signals undergo additional processing operations such as bitwise/logical/mathematical operations and signal conditioning, then functionality is enhanced, but the need for interconnection resources is further compounded
Solution Approach 1:
The patent merges the functionality of dedicated routing interconnects with the output processing logic. By combining the routing function with signal processing operations in an integrated manner, the patent reduces the need for separate interconnection resources while enhancing signal processing capabilities. This merging allows multiple functions to be achieved with fewer discrete components.
Solution Approach 2:
The patent designs the dedicated routing interconnects to serve multiple functions: they provide dedicated input paths to FSBs, support output signal routing, and enable various signal processing operations. This multi-functionality reduces the overall device complexity by eliminating the need for separate dedicated structures for each function.
3Adaptability or versatility
If more interconnection resources are added to support increased FSB functionality, then FSB capabilities are enhanced, but the silicon area cost increases significantly
Solution Approach 1:
The patent segments interconnection resources into dedicated routing interconnects for FSB inputs and general interconnection resources for other routing needs. This segmentation allows the system to achieve enhanced FSB capabilities through targeted, area-efficient dedicated interconnects rather than uniformly increasing all interconnection resources, thereby controlling overall silicon area consumption.
Data Source
AI summary
The present invention, generally speaking, relates to taking advantage of existing outputs from logic groupings that neighbor a digital signal processing block in a programmable logic device to expand the functionality of the digital signal processing block. The outputs from the logic groupings are used as dedicated routing interconnects that provide additional inputs into the digital signal processing block (e.g., into function specific blocks) such that the signal processing block receives additional signals. These additional signals can be input into the signal processing block via the dedicated routing interconnect without significant addition of input interconnection resources that are silicon-area expensive.