Deep Inner Spacer Multi-Gate Transistors for Gate Isolation
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Solution Overview
Problem
Existing multi-gate MOSFET devices, particularly multi-bridge-channel (MBC) transistors, face issues with inner spacer features that do not adequately separate the gate structure from the source/drain features, leading to potential electrical shorts and lattice defects due to strain mismatch between semiconductor layers.
Innovation Solution
The introduction of deep inner spacer features that extend vertically across a buffer layer, separating the gate structure from the source/drain features, and incorporating a vertical stack of germanium-tin (GeSn) or silicon germanium (SiGe) nanostructures to reduce lattice defects and enhance electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate structure extends into the buffer layer to improve gate control, then gate-channel coupling is improved, but electrical shorts occur between gate and source/drain
Solution Approach 1:
The patent introduces an inner spacer feature as an intermediary element positioned between the gate structure and source/drain regions. This inner spacer extends into the buffer layer alongside the gate, maintaining the gate's extended control while preventing direct electrical contact between gate and source/drain, thus resolving the electrical short issue.
Solution Approach 2:
The patent segments the space between gate and source/drain by introducing a distinct inner spacer feature. This segmentation creates separate functional zones: the gate zone for control, the inner spacer zone for isolation, and the source/drain zone for current flow, allowing the gate to extend into the buffer layer without causing shorts.
2Reliability
If the gate structure extends into the buffer layer, then gate control is improved, but lattice defects increase due to silicon-germanium lattice mismatch
Solution Approach 1:
The inner spacer feature acts as a mediator that allows the gate structure to extend into the buffer layer for improved control while preventing the gate from directly interacting with the silicon-germanium interface. This intermediary positioning reduces the propagation of lattice mismatch defects from the buffer layer into the gate structure.
Solution Approach 2:
The patent applies local quality by creating a distinct inner spacer region with specific material properties that differ from both the gate and the buffer layer. This localized structure with optimized properties prevents lattice defects from propagating while maintaining gate control benefits in the extended region.
3Reliability
If inner spacer features are formed to prevent electrical shorts, then gate-source/drain separation is improved, but device complexity increases
Solution Approach 1:
The patent merges the formation of inner spacer features with existing fabrication processes such as the formation of source/drain trenches or buffer layer processing. By combining multiple functions into integrated process steps, the patent reduces overall device complexity despite adding the inner spacer structure for electrical separation.
Data Source
AI summary
The present disclosure provides a semiconductor structure and a method of forming the same. A semiconductor structure according to the present disclosure includes a plurality of nanostructures disposed over a substrate, a plurality of inner spacer features interleaving the plurality of nanostructures. The plurality of nanostructures are arranged along a direction perpendicular to the substrate. The plurality of inner spacer features include a bottommost inner spacer feature and upper inner spacer features disposed above the bottommost inner spacer feature. The first height of the bottommost inner spacer feature along the direction is greater than a second height of each of the upper inner spacer features.