Deep N-Well Isolation for RRAM Leakage and Punch-Through
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Solution Overview
Problem
In resistive random access memory (RRAM) circuits, the decreasing feature size of process nodes leads to increased electric fields, drain-induced barrier lowering (DIBL), and bulk punch-through, making it difficult to reset the memory due to low current flow.
Innovation Solution
The method involves forming a deep N-well region in the substrate to isolate it from the P-well region, allowing separate voltage control in the P-well region. By applying a negative voltage to the P-well region, leakage current is reduced, and during normal operations, a positive voltage is applied to facilitate easy turn-on of the transistor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the feature size of process nodes continues to decrease, then the integration density is improved, but the distance between source end and drain end becomes increasingly short, resulting in enhanced electric field and bulk punch-through
Solution Approach 1:
The patent divides the substrate into isolated regions by introducing deep N-well regions that physically separate the P-well region containing the transistor from the substrate. This segmentation prevents the enhancement electric field from spreading to the substrate, thereby eliminating bulk punch-through while maintaining high integration density achieved through continued feature size reduction.
Solution Approach 2:
The deep N-well region acts as an intermediary barrier between the P-well region and the substrate. By applying a negative voltage to the deep N-well region, the patent creates a potential barrier that blocks the enhancement electric field from reaching the substrate, thus preventing bulk punch-through while allowing the transistor to benefit from scaled feature sizes.
2Length of moving object
If the distance between source end and drain end is shortened, then the device scaling is improved, but the electric field between source end and drain end is enhanced, causing drain-induced barrier lowering
Solution Approach 1:
The deep N-well region serves as an intermediary that isolates the P-well region from the substrate, preventing the enhancement electric field generated by short channel lengths from affecting the substrate. This allows continued device scaling with reduced channel lengths while mitigating the harmful effects of enhanced electric fields through the isolating barrier.
3Ease of operation
If a positive voltage is applied to the P-well region, then the transistor structure is easily turned on, but leakage current increases
Solution Approach 1:
The patent dynamically adjusts the voltage applied to the deep N-well region based on operational requirements. During normal operation, a negative voltage is applied to suppress leakage current. During reset operations, the voltage is adjusted to facilitate transistor turn-on. This dynamic voltage control allows the system to switch between leakage suppression and easy turn-on modes as needed.
Solution Approach 2:
The patent changes the voltage parameter of the deep N-well region from negative during normal operation to positive during reset operations. This parameter change allows the system to first suppress leakage current during normal operation, then facilitate easy turn-on during reset operations by reversing the voltage polarity, thus resolving the contradiction between leakage suppression and operational ease.
4Use of energy by moving object
If the operating voltage is reduced, then the energy consumption is reduced, but the current flowing through the RRAM is low, making it difficult to reset
Solution Approach 1:
The deep N-well region acts as an intermediary that isolates the P-well region from the substrate, preventing voltage division across the transistor during reset operations. By applying a negative voltage to the deep N-well region, the patent ensures that the full operating voltage is available across the RRAM, enabling effective reset even at reduced operating voltages and thus resolving the contradiction between energy consumption and reset effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces leakage current and enhances the turn-on characteristics of the transistor structure, improving the reset operation in RRAM circuits by increasing the turn-on current and reducing the threshold voltage.
Implementation Method 1
forming a deep N-well region in the substrate to isolate it from the P-well region, allowing separate voltage control in the P-well region
Implementation Method 2
By applying a negative voltage to the P-well region, leakage current is reduced
Implementation Method 3
during normal operations, a positive voltage is applied to facilitate easy turn-on of the transistor structure
Data Source
AI summary
A method for operating a memory apparatus, a memory apparatus, a device, and a storage medium are provided. The method includes: providing a semiconductor device including a substrate, a deep N-well region disposed in the substrate, a P-well region disposed in the deep N-well region, and a plurality of transistor structures disposed in the P-well region, where each of the transistor structures includes a gate, a source and a drain; and applying a first voltage to a port of the gate, a second voltage to a port of the deep N-well region, and a third voltage to a port of the P-well region. When a first operation is performed, the first voltage is equal to 0, the second voltage is a positive voltage, and the third voltage is a negative voltage; when a second operation is performed, the first, second and third voltages are positive voltages.