Common Deep N-Well Layout for Compact Multi-Voltage Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices with multiple power domains require large gaps between non-deep wells configured for different power domains, leading to wasted space and increased footprint.
Innovation Solution
Incorporating a deep N-well biased to the greater of the two power supply voltages, allowing for a significantly smaller gap between non-deep wells, thereby reducing the overall area/footprint of the cell region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate non-deep wells are configured for different power domains, then each power domain can be properly isolated, but large gaps are required between the wells leading to increased device footprint
Solution Approach 1:
The patent implements a deep N-well structure that contains multiple non-deep N-wells within it. The first non-deep N-well (for first power domain) and second non-deep N-well (for second power domain) are both formed within the deep N-well, allowing them to be nested together rather than requiring separate locations with large gaps between them. This nesting approach maintains power domain isolation while significantly reducing the overall device footprint.
Solution Approach 2:
The patent transitions from a planar arrangement where non-deep wells would require lateral separation to a vertical arrangement where multiple non-deep wells are stacked within the deep N-well structure. By utilizing the vertical dimension (depth) rather than lateral spacing, the patent achieves both power domain isolation and compact footprint, effectively moving the solution from two-dimensional spacing to three-dimensional nesting.
2Reliability
If large gaps are used between non-deep wells for different power domains, then proper isolation is maintained, but space is wasted and area increases
Solution Approach 1:
The deep N-well serves as a container that holds multiple non-deep N-wells in a nested configuration. The first non-deep N-well and second non-deep N-well are both formed within the boundaries of the deep N-well, eliminating the need for large gaps between them. This nesting structure maximizes space utilization while maintaining the necessary isolation between different power domains through the deep N-well's inherent isolation properties.
Solution Approach 2:
The patent merges multiple non-deep wells that would traditionally require separate locations into a single deep N-well structure. By combining the first non-deep N-well and second non-deep N-well within the same deep N-well, the patent eliminates wasted space while maintaining power domain isolation through the deep N-well's isolation characteristics.
Data Source
AI summary
A semiconductor device includes: a substrate having a first conductivity-type; and a cell region including: a deep well having a second conductivity-type; first and second non-deep wells having the second conductivity-type in corresponding first and second portions of the substrate, the first and second portions of the substrate being in the deep well; and first through fourth transistor-regions, the first and second transistor-regions including transistors having the first conductivity-type, the first and second transistor-regions being correspondingly in the first and second non-deep wells, and the third and fourth transistor-regions including transistors having the second conductivity-type, the third and fourth transistor-regions being corresponding in third and fourth portions of the substrate, the third and fourth portions of the substrate being in the deep well; the first transistor-region being configured for a first power domain; and the second, third and fourth transistor-regions being configured for a second, different, power domain.