Deep-Sub-Tile Mosaicing for Power Grid Design Rule Compliance
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Solution Overview
Problem
Deep-sub-micron integrated circuit designs face challenges in maximizing design layout utilization and manufacturability due to stringent design rules, particularly in metal layers and vias, which are often not recognized by automated tools, leading to time-consuming and labor-intensive design rule checks and potential fabrication defects.
Innovation Solution
A computer-aided design system employing deep-sub-tiling to optimize metal layer mosaic coverage by applying tile, sub-tile, and deep-sub-tile patterns to identify and correct design rule violations, thereby maximizing power grid mosaic coverage while minimizing computation time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If automated design tools are used for metal layer and via design rules, then productivity is improved, but manufacturing precision deteriorates due to unrecognized stringent design rules in deep-sub-micron circuits
Solution Approach 1:
The patent segments the metal layer and via design rule checking into multiple hierarchical levels: global level checking for overall layout compliance, sub-level checking for local via density and spacing, and deep-sub-level checking for individual via and metal feature compliance. This segmentation allows automated tools to systematically address stringent deep-sub-micron design rules that were previously unrecognized, improving both productivity through automation and precision through multi-level verification.
2Manufacturing precision
If manual design rule checking is performed to ensure compliance, then manufacturing precision is improved, but productivity deteriorates due to time-consuming and labor-intensive processes
Solution Approach 1:
The patent implements self-service through automated design rule checking where the EDA tool independently performs multi-level verification without requiring manual intervention. The system automatically applies design rules at global, sub-level, and deep-sub-levels, generates compliance reports, and identifies violations, thereby maintaining high manufacturing precision while dramatically improving productivity by eliminating time-consuming manual checking processes.
3Productivity
If design layout is optimized to maximize utilization, then productivity is improved, but reliability deteriorates due to increased risk of fabrication defects from violated design rules
Solution Approach 1:
The patent implements feedback mechanisms at multiple levels: global feedback reports overall layout compliance, sub-level feedback identifies local via density issues, and deep-sub-level feedback pinpoints specific via and metal feature violations. This multi-level feedback system allows designers to optimize layout utilization while maintaining reliability by systematically identifying and correcting design rule violations that could lead to fabrication defects.
Data Source
AI summary
A computer aided design system can determine coverage of a metal layer mosaic. The system can apply a tile pattern to a design including at least one layer. Then, the system can identify at least one tile of the tile pattern that violates at least one first design rule. After that, the system can apply a sub-tile pattern to an area identified in the identifying the at least one tile of the tile pattern that violates the design rule. The system further can identify at least one sub-tile of the sub-tile pattern that violates at least one second design rule. Finally, the system can apply a deep-sub-tile pattern to an area identified in the identifying the at least one sub-tile of the sub-tile pattern that violates the second design rule.