Deep Trench Capacitor Void Structure for Stress Relief

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Solution Overview

Problem

Conventional deep trench capacitor structures face challenges with increased stress and warpage issues due to deepening trenches, affecting bonding effects and performance, which are not adequately addressed by existing fabrication methods.

Innovation Solution

A semiconductor device with a trench and capacitor structure featuring a void in the capacitor structure, where a material layer seals the top end of the void, reducing stress and enhancing bonding effects by incorporating a void to buffer and absorb stress, thereby improving the capacitor's performance and bonding with other film layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the trench depth is increased to provide higher capacitance value, then the capacitance performance is improved, but the stress in the capacitor structure increases and substrate fracture probability increases

Engineering Contradiction:
Improvecapacitance performanceVSAvoidsubstrate strength
Core Design Contradiction:
ReliabilityVSStrength

Solution Approach 1:

A void structure is formed within the capacitor structure before final assembly, positioned to buffer and absorb stress that develops during operation. This preemptive stress absorption mechanism prevents substrate fracture while maintaining the deep trench configuration needed for high capacitance performance.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

Solution Approach 2:

The void acts as an intermediary element between the deep trench capacitor structure and the substrate, mediating the stress transmission. By introducing this intermediate void space, the direct stress path from the deep trench to the substrate is interrupted, reducing fracture risk while preserving capacitance functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the trench depth is increased to provide higher capacitance value, then the capacitance performance is improved, but warpage degree of the material layer increases and bonding effect deteriorates

Engineering Contradiction:
Improvecapacitance performanceVSAvoidbonding quality
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The void structure is incorporated in advance to compensate for warpage that would otherwise develop in the material layer. By providing this preemptive stress buffer, the material layer maintains better flatness and bonding quality despite the increased trench depth required for high capacitance.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Reliability

If the trench depth is increased to provide higher capacitance value, then the capacitance performance is improved, but the stress in the capacitor structure increases

Engineering Contradiction:
Improvecapacitance performanceVSAvoidinternal stress
Core Design Contradiction:
ReliabilityVSStress or pressure

Solution Approach 1:

A void space is extracted or removed from the capacitor structure, creating an empty region that does not transmit stress. This extracted void volume serves as a stress relief zone, allowing the deep trench configuration to maintain high capacitance while reducing the overall stress state of the structure.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20250359078A1Semiconductor device and method for fabricating the same
Publication Date: 2025.11.20 UNITED MICROELECTRONICS CORP
  • US20250359078A1 patent drawing
  • US20250359078A1 patent drawing
  • US20250359078A1 patent drawing

AI summary

A semiconductor device includes a trench, a capacitor structure and a void. The trench is formed in a substrate. The capacitor structure is disposed in the trench. The void is located in the capacitor structure. A material layer of the capacitor structure is merged in the trench to seal a top end of the void.