Deep Trench Capacitors in Package Substrates for Core Noise Reduction
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Solution Overview
Problem
The increasing dynamic noise (di/dt) and voltage loss in processor cores and ASICs due to faster core clock frequencies and higher current consumption pose a challenge, as traditional decoupling capacitors on the integrated circuit die are limited by die size constraints.
Innovation Solution
Embedding deep trench capacitors in the package substrate rather than on the integrated circuit die, allowing for increased decoupling capacitance without expanding the die size, with capacitors placed on either side of the substrate to address noise frequencies effectively based on load variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If decoupling capacitors are placed on the integrated circuit die, then noise filtering is provided, but die size increases
Solution Approach 1:
The decoupling capacitors are extracted from the integrated circuit die and relocated to the package substrate. This separation allows the die to maintain its compact size while the capacitors are positioned in cavities on the substrate, providing noise filtering functionality without increasing the critical die area.
Solution Approach 2:
The solution transitions from a two-dimensional placement on the die surface to a three-dimensional configuration using cavities in the substrate. By embedding capacitors in vertical cavities and utilizing both top and bottom surfaces of the substrate, the design achieves increased decoupling capacitance without expanding the die footprint.
2Object-affected harmful factors
If capacitor size is increased to address lower frequency noise, then noise filtering effectiveness improves, but more substrate space is required
Solution Approach 1:
The capacitors are nested within cavities formed in the substrate, allowing larger capacitor structures to be accommodated within the substrate volume rather than occupying surface area. This nested configuration enables increased capacitance values for low-frequency noise filtering while maintaining a compact overall package footprint.
Data Source
AI summary
This disclosure relates to deep trench capacitors embedded in a package substrate on which an integrated circuit is mounted. In some aspects, a chip package includes an integrated circuit die that has a power distribution circuit for one or more circuits of the integrated circuit. The chip package also includes a substrate different from the integrated circuit and having a first surface on which the integrated circuit die is mounted and a second surface opposite the first surface. The substrate includes one or more cavities formed in at least one of the first surface or the second surface. The chip package also includes one or more deep trench capacitors disposed in at least one of the one or more cavities. Each deep trench capacitor is connected to the power distribution circuit by conductors.