Deep Trench Isolation for RF SOI Devices
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Solution Overview
Problem
SOI MOS RF switches face challenges with strong coupling between silicon thin film MOSFET transistors and metal interconnect wires and the buried oxide layer, affecting linearity and harmonic distortion without effective RF insulation.
Innovation Solution
A method involving a silicon-on-insulator substrate with shallow trench isolation structures and transistors, followed by forming a deep trench isolation using a hard mask layer and dielectric capping, which reduces substrate coupling and improves electrical characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If shallow trench isolation structures are formed in SOI substrate, then manufacturing process is simplified, but substrate coupling between transistors and buried oxide layer cannot be effectively reduced
Solution Approach 1:
The patent transitions from two-dimensional shallow trench isolation to three-dimensional deep trench isolation that extends through the buried oxide layer to the first semiconductor substrate. This dimensional change enables the isolation structure to reach deeper into the substrate, effectively reducing substrate coupling while maintaining manufacturing feasibility through sequential etching processes.
Solution Approach 2:
The isolation process is segmented into multiple stages: first forming shallow trench isolation structures, then forming deep trench isolation structures that extend deeper into the substrate. This segmentation allows the manufacturing process to address both ease of fabrication and effective substrate coupling reduction by creating isolated regions at different depths.
2Reliability
If deep trench isolation is formed to reduce substrate coupling, then linearity and resonant characteristics improve, but device structure and manufacturing process become more complex
Solution Approach 1:
The patent performs preliminary actions by first forming shallow trench isolation structures and depositing dielectric capping layers before creating the deep trench isolation structures. This preliminary preparation simplifies the overall manufacturing process by establishing a foundation that guides subsequent deep trench formation, reducing the complexity of the complete process.
Solution Approach 2:
The isolation structure employs a nested configuration where shallow trench isolation structures are contained within regions that also contain deep trench isolation structures. The dielectric capping layers are deposited to cover both the shallow and deep trench structures, creating a nested arrangement that achieves effective substrate coupling reduction while organizing the complexity in a systematic manner.
Data Source
AI summary
A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a SOI substrate having shallow trench isolations (STIs) and transistors formed within and on the second semiconductor substrate, respectively. The method also includes forming a hard mask over the first region and removing the STIs, the transistors, the second semiconductor substrate and the buried insulating layer in the second region using the hard mask as a mask, and forming a capping layer covering the deep trench isolation and the second semiconductor substrate including the transistors.