Deep Trench Polysilicon Isolation With Bottom-Up Void-Free Growth
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Solution Overview
Problem
Current deep trench isolation (DTI) structures in integrated chips face issues with void formation during polysilicon growth, leading to compromised mechanical and electrical properties, and require costly and damaging chemical mechanical planarization (CMP) processes to achieve a flat surface.
Innovation Solution
A selective polysilicon growth process is employed that grows polysilicon in a bottom-up direction within the trench, avoiding voids and eliminating the need for CMP by ensuring a flat top surface, thus forming reliable DTI structures that provide effective electrical isolation between semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional polysilicon growth is used to fill deep trenches, then the trench can be filled with polysilicon, but voids form during growth compromising mechanical and electrical properties
Solution Approach 1:
Instead of growing polysilicon from the top surface downward into the trench, the patent inverts the growth direction by growing polysilicon from the bottom of the trench upward. This is achieved by depositing a thin polysilicon layer at the trench bottom first, then performing selective epitaxial growth that propagates upward from this seed layer, filling the trench without forming voids.
Solution Approach 2:
Before performing the selective polysilicon growth, the patent prepares the trench bottom by depositing a thin polysilicon layer that serves as a seed layer. This preliminary action ensures that the subsequent selective growth has a proper nucleation site and grows uniformly upward, preventing void formation during the filling process.
2Reliability
If conventional polysilicon growth is used, then the trench can be filled, but the surface becomes non-planar requiring costly and damaging CMP processes
Solution Approach 1:
The patent inverts the growth approach to achieve planarity. By growing polysilicon from the bottom upward with controlled selective epitaxial growth, the process naturally forms a planar surface at the trench opening. This eliminates the need for subsequent CMP processes that would otherwise be required to flatten the surface.
Solution Approach 2:
The selective polysilicon growth process is self-regulating in terms of surface planarity. As the polysilicon grows upward from the trench bottom, the growth automatically levels the surface, with the polysilicon emerging flush with the surrounding substrate surface without requiring external planarization steps.
3Reliability
If deep trench isolation structures are implemented to provide electrical isolation, then device performance improves, but the manufacturing process becomes more complex and costly
Solution Approach 1:
The patent replaces the mechanical CMP process with a chemically-driven selective epitaxial growth process. Instead of using mechanical abrasion to achieve planarity and proper filling, the process uses controlled chemical vapor deposition and selective epitaxial growth to automatically fill the trench and form a planar surface, thereby eliminating the need for separate CMP steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method efficiently fills trenches with polysilicon, enhancing the mechanical and electrical properties of DTI structures, reducing manufacturing time and cost, and ensuring reliable electrical isolation without the need for CMP, thereby improving device performance and reducing leakage and cross-talk.
Implementation Method 1
growing polysilicon in the trench and between the insulator liners, such that the polysilicon grows from the horizontally extending surface of the substrate towards a top surface, in a second direction normal to the top surface and opposite to the first direction
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip that includes a semiconductor device, a polysilicon isolation structure, and a first and second insulator liner. The semiconductor device is disposed on a frontside of a substrate. The polysilicon isolation structure continuously surrounds the semiconductor device and extends from the frontside of the substrate towards a backside of the substrate. The first insulator liner and second insulator liner respectively surround a first outermost sidewall and a second outermost sidewall of the polysilicon isolation structure. The substrate includes a monocrystalline facet arranged between the first and second insulator liners. A top of the monocrystalline facet is above bottommost surfaces of the polysilicon isolation structure, the first insulator liner, and the second insulator liner.


