Deep Trench Polysilicon Hard Mask Removal via Segmented Etching
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Solution Overview
Problem
Conventional techniques for manufacturing capacitor structures for dynamic random access memory (DRAM) devices face challenges in achieving smaller device sizes with high capacitance values and low leakage characteristics, while also being difficult to manufacture and requiring complex processes.
Innovation Solution
A method involving a semiconductor substrate with a pad oxide layer, nitride layer, and interlayer dielectric layer, using reactive ion etching processes to form trench structures, and protecting the substrate with an oxide layer to prevent damage, followed by forming electrode plates and dielectric layers to complete the capacitor structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional techniques are used to manufacture capacitor structures for smaller device sizes, then device geometry is reduced, but manufacturing complexity increases and process limitations are reached
Solution Approach 1:
The patent segments the trench formation process into two distinct stages: first forming a shallow trench through the interlayer dielectric layer, and then forming a deeper trench extending into the semiconductor substrate. This segmentation allows each etching process to be optimized independently, avoiding the complexity and process limitations associated with attempting to form the entire deep trench structure in a single conventional process step.
2Reliability
If deep trench structures are formed to maintain capacitance in smaller devices, then capacitance values are maintained, but manufacturing difficulty increases
Solution Approach 1:
The patent applies preliminary action by first forming the shallow trench structure through the interlayer dielectric layer before proceeding to form the deeper trench into the substrate. This preliminary structuring creates a foundation that simplifies subsequent processing, allowing the deep trench to be formed more easily while maintaining the required capacitance performance.
Solution Approach 2:
The patent introduces an intermediary structure - the shallow trench formed through the interlayer dielectric layer - that serves as a mediator between the surface-level processing and the deep substrate trench formation. This intermediary structure facilitates easier manufacturing by providing a pre-defined pathway and reducing the complexity of direct deep trench formation.
3Length of stationary object
If reactive ion etching is used to form deep trenches, then trench depth is achieved, but substrate damage occurs
Solution Approach 1:
The patent segments the deep trench formation into two separate etching processes: a first reactive ion etching process that forms a shallow trench through the interlayer dielectric layer, and a second process that completes the deep trench into the substrate. This segmentation prevents excessive substrate damage that would occur if a single deep etching process were used, as each process can be optimized with appropriate etching parameters and depths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances device yields, maintains compatibility with conventional processes, and improves capacitor structure characteristics, particularly for design rules of 0.13 microns and less, without requiring substantial modifications to equipment or processes.
Implementation Method 1
applying a first reactive ion etching process to form a first trench region through a portion of the interlayer dielectric layer
Implementation Method 2
applying a second reactive ion etching process to continue to form a second trench region by removing the oxide layer and removing a portion of the semiconductor substrate
Implementation Method 3
forming an oxide layer overlying at least the exposed surface region of the semiconductor substrate to protect the exposed surface region of the semiconductor substrate
Data Source
AI summary
A method of forming a capacitor structure includes forming a pad oxide layer overlying a substrate, a nitride layer overlying the pad oxide layer, an interlayer dielectric layer overlying the nitride layer, and a patterned polysilicon mask layer overlying the interlayer dielectric layer. The method then applies a first RIE process to form a trench region through a portion of the interlayer dielectric layer using the patterned polysilicon mask layer and maintaining the first RIE to etch through a portion of the nitride layer and through a portion of the pad oxide layer. The method stops the first RIE when a portion of the substrate has been exposed. The method then forms an oxide layer overlying the exposed portion of the substrate and applies a second RIE process to continue to form the trench region by removing the oxide layer and removing a portion of the substrate to a predetermined depth.