Asymmetric Deep-Well IC Structure for Leakage Control
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Solution Overview
Problem
Conventional approaches to reduce current leakage in integrated circuits (ICs) often compromise other attributes such as processing frequency, and are limited by the fundamental concepts of standard cell layouts, which struggle to manage leakage currents effectively while maintaining performance and reliability.
Innovation Solution
The formation of a deep well within a substrate with a well boundary distal to the midpoint, combined with active semiconductor regions of opposing doping types, allows for reduced leakage currents and improved operational reliability without significantly affecting the position and arrangement of nearby logic cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If conventional approaches are used to reduce current leakage in standard cells, then current leakage is reduced, but processing frequency and other device attributes are negatively affected
Solution Approach 1:
The patent applies local quality by creating an asymmetric well structure where the well boundary is positioned distal to the substrate midpoint, specifically extending the well deeper on one side than the other. This localized structural variation allows different regions of the transistor to have different electrical characteristics, enabling leakage reduction in specific areas while preserving processing performance in critical regions.
Solution Approach 2:
The invention fundamentally employs asymmetry by positioning the well boundary distal to the midpoint of the substrate thickness, creating an asymmetric well depth configuration. This asymmetric structure breaks the symmetry of conventional wells, allowing optimized control of electric fields and carrier distribution to reduce leakage without uniformly degrading device performance.
2Ease of manufacture
If standard cell layouts are used, then uniform manufacturing and ease of placement are achieved, but effective management of leakage currents is limited
Solution Approach 1:
The patent changes the geometric parameter of the well structure by positioning the well boundary distal to the substrate midpoint, creating asymmetric well depths. This parameter modification allows the same standard cell layout framework to achieve improved leakage control without requiring fundamental changes to the manufacturing process or cell architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces current leakage in ICs while maintaining or improving operational reliability and frequency, allowing for more efficient logic operations without altering the fundamental layout of the logic cells.
Implementation Method 1
forming a deep well within a substrate having a first doping type, the deep well including a second doping type opposite the first doping type
Implementation Method 2
the body of the transistor (or back gate in the case of SOI technologies) is electrically biased, e.g., to control the threshold voltage of particular transistors in a device
Data Source
AI summary
The disclosure provides integrated circuit (IC) structures and methods to form the same. Methods according to the disclosure may be performed on a substrate having a first doping type, the substrate extending between a first end and a second end. A deep well is formed within the substrate, the deep well including a well boundary defined between the deep well and a remainder of the substrate. The well boundary is horizontally distal to a midpoint between the first end and the second end of the substrate. A first active semiconductor region is formed at least partially over the substrate, and an oppositely-doped second active semiconductor region is formed at least partially over the deep well.