Delay-Cell Digital Logic Controller for Low-Power Glitch Filtering

Solution Overview

Problem

Existing digital logic controllers require a large number of flip-flops to filter glitches, which compromises compact design and increases power consumption, especially in mobile devices.

Innovation Solution

A digital logic controller design that uses a series of delay cells and a single flip-flop to generate time-delayed input signals, coupled with comparators and logic gates to selectively deactivate processing during glitch intervals, reducing the need for multiple flip-flops and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a large number of flip-flops are used to filter glitches, then the circuit reliability is improved, but the device area and power consumption increase

Engineering Contradiction:

Improvecircuit reliabilityVSAvoiddevice area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines multiple delay functions into a single delay element that generates multiple delayed signal versions. Instead of using separate flip-flops for each delay function, the invention merges these functions into one component that feeds delayed signals to a counter, thereby reducing the total number of components while maintaining glitch filtering capability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a counter as an intermediary component between the delay element and the output logic. This counter receives multiple delayed signal versions and processes them to generate the final output, acting as a mediator that eliminates the need for multiple flip-flops while maintaining reliable glitch filtering through sequential signal processing.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If a large number of flip-flops are used to filter glitches, then the circuit reliability is improved, but the power consumption increases

Engineering Contradiction:

Improvecircuit reliabilityVSAvoidpower consumption

Core Design Contradiction:

ReliabilityVSUse of energy by stationary object

Solution Approach 1:

The patent combines multiple delay functions into a single delay element that generates multiple delayed signal versions. Instead of using separate flip-flops for each delay function, the invention merges these functions into one component that feeds delayed signals to a counter, thereby reducing the total number of components while maintaining glitch filtering capability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The patent introduces a counter as an intermediary component between the delay element and the output logic. This counter receives multiple delayed signal versions and processes them to generate the final output, acting as a mediator that eliminates the need for multiple flip-flops while maintaining reliable glitch filtering through sequential signal processing.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If multiple flip-flops are used for noise filtering, then the glitch filtering capability is improved, but the device complexity increases

Engineering Contradiction:

Improveglitch filtering capabilityVSAvoiddevice complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple delay functions into a single delay element that generates multiple delayed signal versions. Instead of using separate flip-flops for each delay function, the invention merges these functions into one component that feeds delayed signals to a counter, thereby reducing the total number of components while maintaining glitch filtering capability.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The delay element in the patent serves multiple functions simultaneously: it generates multiple delayed signal versions, provides noise filtering, and enables the counter to process signals sequentially. This multi-functional design eliminates the need for separate components for each function, thereby reducing device complexity while maintaining effective glitch filtering.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentEP4350995A1Digital logic controller

Publication Date: 2024.04.10 EM MICROELECTRONIC-MARIN

Figure 1
Figure 2

AI summary

The present disclosure relates to digital logic controller (10). The digital logic controller (10) comprising: - a first delay cell (14) connectable to a signal input (11) and operable to generate a first time delayed input signal, - a second delay cell (16) connectable to the signal input (11) and operable to generate a second time delayed input signal, - a counter (18) connectable to the signal input (11) via the first delay cell (14), - two logic units (20, 21) to generate reset signal by one of logic units and to generate set signal by the other of logic units, and connected between the set of delay cells (14, 15, 16, 17) and a flip-flop (22) operable to generate a counter valid signal at a flip-flop output (24), - a first comparator (30) connected to an output of the counter (18) and operable to compare a counter output signal with a first target, - a first logic gate (31) connected to the flip-flop output (24), connected to the first comparator (30) and operable to temporally deactivate processing of the counter output signal.