Fast-Setting Delay Circuit With Switched Bias Clocking
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing delay circuits face challenges in quickly setting the bias voltages for delay lines, leading to high latency and power consumption, especially during idle periods in systems like PHY receivers and transmitters.
Innovation Solution
A fast-setting delay circuit design that includes a bias generator with a multiplexer to switch between a high-frequency fast clock signal and a lower-frequency clock signal, reducing the settling time of bias voltages and allowing for faster power-up and reduced power consumption by using a multiplexer to selectively input these signals based on a control signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If a bias generator uses a single clock signal to bias a delay line, then the circuit structure is simple, but the settling time is long and power consumption is high during idle periods
Solution Approach 1:
The patent applies dynamics by making the clock signal frequency adjustable based on operational mode. The bias generator dynamically switches between a first clock signal (higher frequency) during active periods to reduce settling time, and a second clock signal (lower frequency) during idle periods to reduce power consumption. This dynamic adaptation resolves the contradiction between fast settling and low power consumption without requiring a completely complex circuit structure.
Solution Approach 2:
The patent changes the clock signal frequency parameter based on the operational state of the delay circuit. By using a multiplexer to select between different clock signals with different frequencies, the system optimizes the balance between settling time and power consumption. The higher frequency clock reduces settling time when needed, while the lower frequency clock reduces power consumption during idle periods.
2Speed
If a bias generator uses a high-frequency clock signal to reduce settling time, then the latency is reduced, but the power consumption increases during idle periods
Solution Approach 1:
The system dynamically adjusts the clock signal frequency based on whether the delay circuit is in an active or idle state. During active periods, the higher frequency clock signal is used to achieve fast bias generation and low latency. During idle periods, the system switches to a lower frequency clock signal to minimize power consumption. This dynamic behavior resolves the contradiction between speed and energy usage.
Solution Approach 2:
The patent implements periodic action by using different clock frequencies for different operational phases. The multiplexer selectively applies the first high-frequency clock signal during periods when fast settling is needed, and the second low-frequency clock signal during idle periods. This periodic switching between different operational modes optimizes both speed and power consumption.
3Stability of the object's composition
If the delay circuit maintains bias voltages continuously, then the delay performance is stable, but the power consumption is high during idle periods
Solution Approach 1:
The patent applies dynamics by adjusting the clock signal frequency based on the operational state. During active periods, the higher frequency clock maintains stable bias voltages for optimal delay performance. During idle periods, the system switches to a lower frequency clock that consumes less power while maintaining sufficient bias stability. This dynamic approach resolves the contradiction between stability and power consumption.
Data Source
AI summary
In certain aspects, a delay circuit includes a delay line including a bias input. The delay circuit also includes a bias generator including a clock input, and a bias output, wherein the bias output of the bias generator is coupled to the bias input of the delay line. The delay circuit further includes a multiplexer including a first input, a second input, and an output, wherein the first input of the multiplexer is configured to receive a first clock signal, the second input of the multiplexer is configured to receive a second clock signal, and the output of the multiplexer is coupled to the clock input of the bias generator.