Transmission TRIZ Cases

Dynamic channel bonding lets a programmable NoC match protocol bandwidth needs and power-gate unused paths to improve utilization and cut power.

A direct sampling base station receiver corrects intermodulation distortion in digital baseband while leaving harmonic distortion untouched to save power.

A hybrid suppression circuit enables single-wire full-duplex die-to-die links across independent clocks and supply voltages while reducing interference.

Coherent averaging turns continuous wave spurs into periodic signals for digital cancellation, easing RF ADC isolation and preserving receiver range.

Temperature-proportional current and driving voltage preserve transmission quality at high heat while cutting power use at lower temperatures.

By bonding physical NOC channels to match protocol bandwidth, the design improves utilization and power-gates unused paths.

Balun placement and power-line routing isolate switchable supply noise from the matching circuit, preserving RF module characteristics.

Threshold-controlled AGC in an RF envelope detector prevents saturation from amplitude swings and interference while preserving clear data recovery.

Separate local oscillators at the input and output mixers let one band select filter cover multiple channels while compensating thermal drift.

Waveform shaping pre-compensates ISI in 10BASE-T transmission by adjusting digital codes to preserve signal integrity over long cables.

An SIW filter embedded between low-noise amplifier stages improves image rejection while cutting shielding, mass, and parasitic coupling.

Switching between mixer-first and amplifier-first paths helps receivers handle jammer interference while limiting power use and signal loss.

Using a very-low intermediate frequency stage, the transmitter suppresses LO leakage at low output power and protects in-band emission compliance.

An analog integrator captures DAC timing and amplitude errors, enabling high SFDR at lower sampling rates with less digital logic and power.

A receiver switches from one ADC to interleaved ADC cores when OOB blockers appear, improving SNR while avoiding constant high power draw.

Selective gate-width sizing in series and parallel switch paths cuts passband loss while preserving RF filter power durability.

FPGAs and external memory add deep buffering and packet scheduling to data planes, easing circuit load while enforcing QoS policies.

Analog subtraction removes the intended transmit signal before ADC conversion, easing dynamic range limits for self-interference cancellation.

Electromagnetic coupling between inductors and anti-parallel diodes suppresses out-of-band signals while reducing filter parts.

A programmable NOC adjusts data width to match protocol bandwidth, bonds channels as needed, and power-gates unused lanes to reduce waste.

Multiple digital up-converter chains split and recombine concurrent bands, easing FPGA bandwidth limits while keeping radios frequency-flexible.

A switch and transistor control path diverts reflected RF power to a load, protecting the LNA during TDD transmit and receive switching.

A transistor-driven switch routes reflected RF energy to a load during TDD transmission, protecting the LNA from high-power damage.

Modified bit weights in post-processing offset switch leakage decay in switched-capacitor SAR-ADCs, improving output accuracy and uniformity.

A stacked phased array element shares one DC current path across phase rotation and sideband correction to cut power use and extend battery life.

Median filtering isolates Gibbs sinc lobes in frequency-domain signals, enabling earlier detection of narrow pulses and abrupt phase changes.

FPGAs redirect unmatched data-plane traffic to hash-addressable external memory, expanding lookup capacity while supporting QoS scheduling.

Different switch stack counts match local voltage in an RF filter, preserving power durability while limiting size and passband loss.

A switch-capacitor series arm lets an RF filter shift attenuation poles while limiting high-edge passband loss and bulk wave loss.

Combines integer division, phase shifting, pulse swallowing, and multiplexing to generate precise high-speed fractional clock signals.

A multiplexer switches the bias generator between fast and slow clocks to cut delay-line settling time and idle power.

An integrated wireless communication block lets programmable logic communicate directly with remote systems without host-system dependency.

A switched resonator branch repositions attenuation poles to tune RF filter bands while limiting insertion loss and edge attenuation degradation.

n+1 calibration measurements adjust SAR ADC decision thresholds to estimate split-capacitor cell weights, including the hard-to-measure LSB.

Baseband Hartley conversion and phase-slope compensation cancel wideband RF interferers while preserving receiver power handling and noise figure.

Temporary short-circuit discharge clears residual filter signals, cutting transceiver RX-to-TX transition time and avoiding erroneous transmission.

A two-stage DAC resistor network raises output impedance to cut thermal noise transfer and improve ENOB, SNDR, and RxBN.

Variable capacitor tuning shifts an FBAR receiver off its transmit frequency, enabling full-duplex RF reception with lower attenuation.

Fractional clock division and lower timing rates generate quadrature clocks with lower power, simpler timing circuits, and moderate spur performance.

One IF-stage converter adjusts local-signal frequencies to handle multiple RF bands, reducing duplicate hardware and band-specific management.

A middleware layer keeps a consistent address and overlaps old and new network links to avoid application data interruption during handover.