Fractional Clock Divider Using Phase Shift and Pulse Swallowing
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Solution Overview
Problem
Current electronic signal generation technologies face challenges in creating high-speed clock signals for integrated circuits, particularly in achieving fractional frequency division efficiently, which is crucial for advanced electronics like computers and IoT devices, as existing methods lack flexibility and precision in generating diverse clocking signals for various applications.
Innovation Solution
A fractional frequency divider is introduced, comprising an integer divider, a pulse swallower, a latch, and a multiplexer, which operates in two modes to achieve fractional division by adjusting the integer divisor and phase shifting, enabling precise control over the output signal frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If integer division is used to generate clock signals, then the device complexity is reduced, but the frequency division precision is insufficient for fractional frequencies
Solution Approach 1:
The fractional frequency divider is segmented into multiple functional blocks: integer divider, pulse swallower, phase shifter, and multiplexer. Each block performs a specific function, allowing the system to achieve fractional division precision through coordinated operation of simpler sub-components rather than requiring a single complex fractional divider circuit.
Solution Approach 2:
The system dynamically switches between different integer divisors (N and N+1) and adjusts phase shifts based on the fractional frequency requirement. The pulse swallower dynamically controls the timing of input pulses to achieve the desired fractional division ratio, enabling adaptive frequency synthesis without fixed hardware constraints.
2Adaptability or versatility
If multiple clock signals are generated through frequency division, then the adaptability for different applications is improved, but the device complexity increases
Solution Approach 1:
The fractional frequency divider is designed as a universal circuit that can generate multiple different clock frequencies from a single input clock signal. By adjusting the fractional division ratio and phase shift parameters, the same circuit serves multiple applications including 10G Ethernet, PCIe, and other high-speed interfaces, eliminating the need for separate clock generation circuits for each application.
3Speed
If high-speed clock signals are generated, then the performance of electronic devices is improved, but the precision and flexibility of frequency control are reduced
Solution Approach 1:
The system uses feedback mechanisms where the output clock signal characteristics are monitored and used to adjust the division ratio and phase shift parameters. This closed-loop control ensures that even at high speeds, the generated clock signals maintain precise frequency relationships required for synchronous operation in high-speed digital systems.
Data Source
AI summary
A fractional divider is described herein which effectively performs an integer division followed by phase shifting, pulse swallowing, and/or multiplexing to realize a fractional divisor. The fractional divider divides an input clocking signal by a first integer divisor in a first mode of operation or by a second integer divisor in a second mode of operation to provide a first phase of a divided digital signal. Thereafter, the fractional divider shifts the first phase of the divided digital signal to provide a second phase of the divided digital signal in the first and second modes of operation. Finally, the fractional divider synchronizes an output clocking signal to the first phase of the divided digital signal and the second phase of the divided digital signal in the first and second modes of operation.