SAR-ADC Bit Weight Compensation for Leakage-Induced Signal Decay
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-performance SAR-ADCs face inaccuracies due to signal decay caused by finite off-resistance of switches, leading to reduced accuracy and non-uniform digital output distributions, which affects the bit weights and subsequent conversion processes.
Innovation Solution
A post-processing unit is introduced to determine bit weights based on the clock signal rate and a parameter representing the signal decay time constant, compensating for errors by recombining bits using modified weights that depend on the clock frequency, thereby correcting for signal decay and improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a switched-capacitor SAR-ADC is used for high-speed conversion, then conversion speed is improved, but signal decay due to finite off-resistance of switches causes reduced accuracy
Solution Approach 1:
The patent applies feedback by measuring the actual statistical distribution of digital output words and using this information to adjust and recalculate bit weights iteratively. The post-processing unit continuously monitors the output distribution and feeds this information back to refine the weighting factors, thereby compensating for signal decay effects while maintaining high conversion speed.
Solution Approach 2:
The patent changes the bit weight parameters dynamically based on observed output statistics. Instead of using fixed ideal bit weights, the system adjusts the weighting factors according to the actual signal decay characteristics measured during operation, allowing the ADC to adapt to varying conditions and maintain accuracy at high conversion speeds.
2Manufacturing precision
If ideal bit weights are used in post-processing, then the digital output distribution should be uniform, but signal decay causes non-uniform distribution
Solution Approach 1:
The system uses feedback by collecting statistics from the actual digital output words and comparing the observed distribution against the expected uniform distribution. This statistical feedback is then used to iteratively adjust the bit weights, creating a closed-loop system that continuously corrects for signal decay effects and restores output uniformity.
Solution Approach 2:
The patent performs preliminary calibration by gathering output statistics and determining adjusted bit weights before actual conversion operations. This preliminary action establishes the correct weighting factors that compensate for signal decay, ensuring that subsequent conversions produce uniformly distributed outputs without requiring real-time correction during each conversion cycle.
3Measurement precision
If signal decay compensation is implemented through post-processing with adjusted bit weights, then output accuracy is improved, but device complexity increases
Solution Approach 1:
The patent replaces complex hardware compensation circuits with a software-based post-processing approach. Instead of modifying the physical ADC structure or adding analog compensation components, the system uses digital signal processing and statistical analysis to compensate for signal decay, significantly reducing device complexity while maintaining accuracy improvement.
Data Source
AI summary
An analog-to-digital conversion circuit (100) is disclosed. It comprises a switched-capacitor SAR-ADC, (110) arranged to receive an analog input signal (x(t)) and a clock signal, to sample the analog input signal (x(t)), and to generate a sequence (W(n)) of digital output words corresponding to samples of the analog input signal (x(t)), wherein the SAR-ADC (110) is arranged to generate a bit of the digital output word per cycle of the clock signal. It further comprises a clock-signal generator (120) arranged to supply the clock signal to the SAR-ADC (110), and a post-processing unit (140) adapted to receive the sequence (W(n)) of digital output words and generate a sequence of digital output numbers (y(n)), corresponding to the digital output words, based on bit weights assigned to the bits of the digital output words. The bit weights are selected to compensate for a decay of a signal internally in the SAR-ADC (110).