FPGA-Augmented Data Plane Buffering and QoS Scheduling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need for enhanced data plane circuit functionality to manage increasing data message forwarding operations efficiently, as existing circuits struggle to handle the demands of robust data message processing and quality of service policies effectively.
Innovation Solution
The integration of field programmable gate arrays (FPGAs) and external memories within the data plane circuit to implement deep buffers and scheduling mechanisms, allowing for flexible configuration and efficient data message processing and forwarding through the network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data plane circuits are configured to perform robust data message forwarding operations and quality of service policies, then data message processing capability is improved, but circuit resource demand increases and existing circuits become overwhelmed
Solution Approach 1:
The patent segments the data plane circuit functionality by introducing field programmable circuits that can be dynamically configured to handle specific forwarding operations and quality of service policies. This segmentation allows the circuit to be divided into reconfigurable functional units that can be independently optimized and managed, preventing resource overwhelm while maintaining high processing capability.
Solution Approach 2:
The patent implements dynamic reconfigurability through field programmable gate arrays (FPGAs) that allow the data plane circuit to adapt its functionality in real-time. The circuit can be dynamically reconfigured to perform different forwarding operations, handle varying traffic loads, and enforce quality of service policies as needed, enabling the system to maintain high productivity without permanent resource over-provisioning.
2Adaptability or versatility
If field programmable circuits are integrated to augment data plane functionality, then adaptability and versatility are improved, but device complexity increases
Solution Approach 1:
The patent employs field programmable circuits that serve multiple functions within the data plane. These circuits can be reconfigured to perform various forwarding operations, implement different quality of service policies, and handle diverse traffic types, providing universal functionality that reduces the need for multiple dedicated circuits and thereby managing complexity while enhancing adaptability.
Solution Approach 2:
The patent introduces field programmable circuits as intermediary elements between the control plane and the fixed-function data plane hardware. These intermediary circuits provide a flexible layer that can be programmed to implement specific forwarding behaviors and quality of service mechanisms, bridging the gap between static hardware and dynamic requirements without directly complicating the core data plane architecture.
Data Source
AI summary
Some embodiments provide novel circuits for augmenting the functionality of a data plane circuit of a forwarding element with one or more field programmable circuits and external memory circuits. The external memories in some embodiments serve as deep buffers that receive through one or more FPGAs a set of data messages from the data plane (DP) circuit to store temporarily. In some of these embodiments, one or more of the FPGAs implement schedulers that specify when data messages should be retrieved from the external memories and provided back to the data plane circuit for forwarding through the network. For instance, in some embodiments, a particular FPGA can perform a scheduling operation for a first set of data messages stored in its associated external memory, and can direct another FPGA to perform the scheduling operation for a second set of data messages stored in the particular FPGA's associated external memory. Specifically, in these embodiments, the particular FPGA determines when the first subset of data messages stored in its associated external memory should be forwarded back to the data plane circuit to forward to data messages in the network, while directing another FPGA to determine when a second subset of data messages stored in the particular FPGA's external memory should be forwarded back to the data plane circuit.