Selective Time-Interleaved ADC for OOB Blocker Aliasing
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Solution Overview
Problem
Conventional receiver systems face challenges in mitigating the reduction in signal-to-noise ratio (SNR) due to out-of-band (OOB) blocker aliasing, particularly in higher-order Nyquist zones, which can lead to significant power dissipation and increased costs, and existing solutions like high-speed ADCs and high-order analog anti-aliasing filters are inefficient and costly.
Innovation Solution
The implementation of selective time-interleaved analog-to-digital conversion (ADC) techniques that dynamically scale sampling rates based on the presence of OOB blockers, allowing the system to operate in two modes: a normal mode and a blocker mode, where additional ADC cores are enabled to effectively reject OOB signals by doubling the sampling rate and using a single common digital signal processing circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If high-speed ADCs are used to reject OOB blockers, then SNR performance is improved, but power dissipation and implementation costs increase
Solution Approach 1:
The patent implements dynamic switching between single-ADC and time-interleaved ADC modes based on the presence of OOB blockers. The system monitors for blocker conditions and activates additional ADC cores only when needed, making the sampling rate adaptive rather than continuously high-speed. This resolves the contradiction by maintaining high SNR performance only when blockers are present while reducing power consumption during normal operation.
Solution Approach 2:
The system changes the sampling rate parameter dynamically - operating at a lower rate during normal conditions and switching to a higher rate (double the sampling rate) when OOB blockers are detected. This parameter change allows the system to achieve high SNR performance only when necessary, thereby reducing overall power dissipation while maintaining measurement precision when required.
2Measurement precision
If high-order analog anti-aliasing filters are used to mitigate OOB blocker aliasing, then SNR performance is improved, but device complexity and costs increase
Solution Approach 1:
The patent replaces complex high-order analog anti-aliasing filters with a time-interleaved ADC architecture. Instead of using sophisticated analog filtering circuitry to reject OOB blockers, the system uses multiple ADC cores operating in parallel with different sampling phases to achieve blocker rejection in the digital domain. This substitution reduces analog filter complexity while maintaining or improving SNR performance.
Solution Approach 2:
The system dynamically activates additional ADC cores only when OOB blockers are detected, rather than continuously operating complex filtering circuits. This dynamic approach reduces the effective device complexity by using simpler ADC structures that are activated on-demand, replacing the need for continuously active high-order analog filters.
3Measurement precision
If time-interleaved ADCs operate continuously at high sampling rates, then OOB blocker rejection is improved, but energy efficiency deteriorates
Solution Approach 1:
The patent implements periodic monitoring for OOB blocker conditions and activates time-interleaved ADC operation only during periods when blockers are present. The system transitions between single-ADC and multi-ADC modes based on periodic assessment of the signal environment, achieving blocker rejection only when needed rather than continuously. This periodic activation dramatically improves energy efficiency while maintaining blocker rejection capability.
Solution Approach 2:
The sampling rate and ADC core activation are made dynamic rather than static. The system adjusts its operating mode based on real-time detection of OOB blockers, switching between low-power single-ADC mode and high-performance time-interleaved mode. This dynamic adaptation resolves the contradiction by maintaining blocker rejection performance only when required, thereby preserving energy efficiency during normal operation.
Data Source
AI summary
Technologies directed to a receiver circuit with selective time-interleaved analog-to-digital converters (ADCs) are described. The receiver circuit includes a first ADC, a second ADC, and a digital processing circuit coupled to the first ADC and second ADC that operates in a first mode or a second mode. In the first mode the first ADC receives a first signal and generates first samples at a first sampling frequency. The digital processing circuit processes the first samples. In the second mode, the first ADC and the second ADC both receive a second signal and collectively generate second samples at a second sampling frequency that is greater than the first sampling frequency. The digital processing circuit processes the second samples.