FPGA Data Plane Offload Using Hash-Addressable External Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
There is a need for enhanced data plane circuit functionality to manage increasing data message forwarding operations efficiently, as existing circuits struggle to handle the demand for robust data message processing and quality of service policies.
Innovation Solution
The integration of field programmable gate arrays (FPGAs) and external memories within the data plane circuit to implement deep buffers and schedulers, allowing for temporary storage and strategic retrieval of data messages, along with the use of hash-addressable tables for efficient message processing and routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If field programmable circuits and external memory circuits are integrated to augment data plane functionality, then the data message processing capability and quality of service management are improved, but the device complexity increases
Solution Approach 1:
The system is divided into distinct functional modules: data plane circuit for message forwarding, field programmable circuits for scheduling and buffering control, and external memory circuits for deep buffering. This segmentation allows each component to specialize in specific tasks, improving overall processing capability while managing complexity through modular design.
Solution Approach 2:
The field programmable circuits serve multiple functions: they act as interfaces between the data plane and external memories, implement scheduling operations for multiple data message subsets, and manage buffering operations. This multi-functionality increases productivity without requiring separate dedicated circuits for each function.
2Reliability
If deep buffers are implemented using external memories to store data messages temporarily, then the quality of service management and message prioritization are improved, but the loss of time for message retrieval and scheduling increases
Solution Approach 1:
Data messages are pre-categorized and organized in the external memory buffers according to their quality of service requirements and priority levels before actual forwarding is needed. The field programmable circuits perform scheduling operations in advance, preparing message subsets for efficient retrieval without requiring complex real-time decision-making during the critical forwarding path.
3Adaptability or versatility
If multiple FPGAs are used to implement schedulers for different data message subsets, then the adaptability and versatility of the data plane are improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The system uses field programmable circuits that can be dynamically reconfigured to implement different scheduling algorithms and buffer management strategies. This dynamic adaptability allows the data plane to handle various quality of service requirements and traffic patterns without requiring physical hardware changes, achieving versatility while simplifying manufacturing compared to fixed-function hardware.
Data Source
AI summary
Some embodiments use one or more FPGAs and external memories associated with the FPGAs to implement large, hash-addressable tables for a data plane circuit. These embodiments configure at least one message processing stage of the DP circuit to store (1) a first plurality of records for matching with a set of data messages received by the DP circuit, and (2) a redirection record redirecting data messages that do not match the first plurality of records to a DP egress port associated with the memory circuit. These embodiments configure an external memory circuit to store a larger, second set of records for matching with redirected data messages received through the DP egress port associated with the memory circuit. This external memory circuit is a hash-addressable memory in some embodiments. To determine whether a redirected data message matches a record in the second set of record, the method of some embodiments configures an FPGA associated with the hash-addressable external memory to use a collision free hash process to generate a collision-free, hash address value from a set of attributes of the data message. This hash address value specifies an address in the external memory for the record in the second set of records to compare with the redirected data message.