Delay Circuit Jitter Analysis for Single-Gate Measurement
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Solution Overview
Problem
Conventional methods for measuring clock jitter in semiconductor devices face challenges in accurately measuring jitter at the single logic gate level due to the nature of ring oscillators and delay circuits, which complicates the prediction of noise characteristics and system performance.
Innovation Solution
A jitter analyzing apparatus comprising a first and second delay circuit with different delay values, where the test device measures the jitter component by comparing the output clocks from these circuits, allowing for precise analysis of jitter at the single logic gate level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If ring oscillators are used for noise measurement, then propagation delay can be measured, but jitter is superimposed and additional circuits are required, making it impossible to measure jitter at a single logic gate level
Solution Approach 1:
The invention divides the delay circuit into multiple identical logic gate stages (first delay circuit with N stages, second delay circuit with M stages). By segmenting the total delay into discrete, identical units, the jitter contribution of each individual logic gate can be isolated and measured, enabling single logic gate level analysis without requiring complex additional jitter extraction circuits.
Solution Approach 2:
The invention creates multiple copies of identical logic gate circuits (first delay circuit and second delay circuit with the same logic gate type but different numbers of stages). These copied circuits provide statistically independent jitter samples that can be processed to extract the jitter component of a single logic gate, avoiding the need for complex de-embedding techniques.
2Measurement precision
If delay circuits are used to measure jitter, then the overall jitter can be converted into a digital signal, but it becomes difficult to de-embed components and measure jitter at the single logic gate level
Solution Approach 1:
By segmenting the delay circuit into N identical stages in the first delay circuit and M identical stages in the second delay circuit, the total jitter measurement can be divided into contributions from individual stages. The jitter component of a single logic gate is calculated by dividing the measured jitter by the number of stages, enabling precise single-gate analysis without complex de-embedding.
Solution Approach 2:
The invention changes the parameter of delay circuit configuration by using two different numbers of logic gate stages (N and M) in the first and second delay circuits respectively. This parameter variation creates a system of equations that can be solved to extract the single logic gate jitter component, simplifying the measurement process compared to traditional de-embedding methods.
3Measurement precision
If high-resolution time to digital converters are used for jitter measurement, then measurement precision is improved, but area constraints on on-chip or TEG space make them difficult to mount
Solution Approach 1:
The invention replaces the expensive, area-consuming high-resolution TDC with a simpler measurement approach using standard delay circuits and basic timing measurements. The multiple delay circuits with different stage counts provide sufficient measurement resolution through statistical analysis, eliminating the need for large-area TDC hardware while maintaining measurement precision.
Data Source
AI summary
A jitter analyzing apparatus may include a first delay circuit configured to delay a reference clock to output a first clock, a second delay circuit configured to delay the reference clock to output a second clock having a delay value greater than the first delay circuit, and a test device configured to measure a jitter component of the first and second delay circuits by measuring the first clock and the second clock.