Programmable Delay Circuit Self-Test for Faster IC Validation
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Solution Overview
Problem
Conventional testing methods for integrated circuits, particularly analog circuits, are time-consuming and prone to errors due to reliance on external test setups, which introduce variability and require extensive setup times and resource utilization, especially in complex ICs used in critical applications like automotive systems.
Innovation Solution
Integrated circuits are equipped with an analog delay circuit, a sampler register, and a test circuit (BIST) that iterates through delay values to determine if the circuit meets a predetermined criterion, reducing the need for external configuration and minimizing test time and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external test setup is used to test integrated circuits, then testing can be performed with standard equipment, but test time increases due to setup time and settling time
Solution Approach 1:
The patent implements built-in self-test (BIST) functionality where the integrated circuit tests itself using an internal test circuit and sampler register. The circuit generates test signals internally and compares delayed signal phases against reference phases, eliminating the need for external test equipment setup and reducing test time while maintaining reliability.
Solution Approach 2:
The patent pre-configures test circuits, sampler registers, and delay phases within the integrated circuit before external testing is needed. The test architecture is built-in during manufacturing, so no external setup or configuration is required at test time, directly reducing setup time and settling time associated with external equipment.
2Reliability
If external test setup is used, then standard testing procedures can be followed, but variability increases introducing errors during testing
Solution Approach 1:
The BIST functionality allows the circuit to perform self-diagnosis without external equipment variability. Internal reference signals and controlled delay phases provide stable, repeatable test conditions that eliminate the variability introduced by external instruments, thereby reducing testing errors.
Solution Approach 2:
The patent introduces an internal sampler register and test circuit as intermediaries between the signal processing path and the comparison function. These internal components provide controlled, stable reference signals that mediate the testing process, eliminating the harmful variability of external test equipment.
3Adaptability or versatility
If test program is written to control external test setup, then specific test techniques can be implemented, but complexity of setup increases
Solution Approach 1:
The integrated circuit includes built-in test control logic that automatically executes test sequences without requiring external programming. The test circuit iterates through delay values and compares phases automatically, reducing setup complexity while maintaining the ability to perform specific test techniques through internal configuration.
Solution Approach 2:
The patent provides programmable delay phases that can be configured through internal control signals. Instead of requiring complex external test programs to adjust parameters, the test circuit can modify delay values internally, simplifying the setup while maintaining adaptability for different test scenarios.
4Reliability
If external test equipment is used, then comprehensive testing can be performed, but resource utilization increases
Solution Approach 1:
The BIST functionality enables the integrated circuit to perform comprehensive self-testing without requiring external test equipment. The internal test circuit, sampler register, and delay phases work together to provide complete testing capability, significantly reducing resource consumption while maintaining testing completeness.
Data Source
AI summary
An integrated circuit includes a test circuit, and an analog delay circuit and a sampler register, each configured to receive a signal. The delay circuit includes a configuration input and phases with a final phase. The sampler register includes result outputs and delay inputs that are each coupled to a respective delay output of the phases. The sampler register is configured to output a sample signal indicating a relationship between the signal and at least the final phase of the phases. The integrated circuit further includes a test circuit that includes a configuration output coupled to the configuration input of the delay circuit, and result inputs coupled to the result outputs of the sampler register. The test circuit is configured to iterate through selected values to test the delay circuit and determine that the delay circuit passes the test when the relationship matches a predetermined criterion.