Delay Circuit State Transition Design for Accurate Time Digitizing

The patent merges the high-frequency counter and ring oscillator into a unified state transition section where they share common timing references and control signals. The counter and oscillator are synchronized through a common clock signal, ensuring that coarse and fine measurements are taken at precisely aligned time points, thereby eliminating the independence-induced timing fluctuations that cause measurement errors.

The patent implements feedback mechanisms where the state information from the ring oscillator is continuously monitored and used to adjust the counting operation of the high-frequency counter. The latched state information provides feedback about the current oscillator phase, which is used to synchronize the counter operation, ensuring that measurements are taken at consistent timing points and preventing the acquisition of wrong state information.

The patent segments the delay function into discrete delay elements arranged in a tapped delay line structure. Each delay element provides a specific time delay, and the taps allow selection of different delay points. This segmentation enables flexible state capture at multiple time points while maintaining a modular and organized circuit structure, making the complexity manageable through systematic design.

The tapped delay line structure serves multiple functions: it provides time-delayed versions of the input signal for different measurement purposes, enables multi-point state capture, and can be used for both coarse and fine measurements. This multi-functionality reduces the need for separate circuits for different timing operations, thereby managing overall circuit complexity while maintaining versatility.