Programmable Delay Clocking for Sequential Logic Timing Margin
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Solution Overview
Problem
In sequential logic systems, achieving optimal timing margins is challenging due to uncertainties in clock skew and signal delays, particularly when timing blocks are far apart, leading to increased register-to-register delays and potential logic errors from cross-coupling capacitance, which existing methods like logic partitioning and signal re-routing are inadequate to address effectively.
Innovation Solution
A sequential logic circuit with programmable delay circuits that introduce a delayed clock signal to control register-to-register delays and minimize cross-coupling capacitance by staggering the operation of registers through additional clock signals with fixed delays, allowing for flexible timing adjustments without relocating combinational logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If timing blocks are located far apart to reduce interference, then cross-coupling capacitance is reduced, but clock skew and signal delay uncertainty increase
Solution Approach 1:
The patent introduces a programmable delay circuit that dynamically adjusts the clock signal timing based on the actual timing requirements of the sequential logic circuit. This allows the system to adapt to varying timing conditions and optimize the timing margin without requiring fixed physical positioning of timing blocks.
Solution Approach 2:
The patent changes the timing parameter of the clock signal by introducing a programmable delay. This delay parameter can be adjusted to compensate for clock skew and signal delay variations, thereby maintaining adequate timing margin even when timing blocks are located far apart.
2Reliability
If logic partitioning is used to reduce register-to-register delay, then timing margin is improved, but device complexity increases
Solution Approach 1:
The patent introduces a programmable delay circuit as an intermediary element that mediates the timing relationship between registers. This intermediary provides precise timing control without requiring complex logic partitioning, thereby improving timing margin while minimizing additional complexity.
3Reliability
If multiple rounds of iteration are performed to optimize timing, then timing goals are achieved, but development time increases
Solution Approach 1:
The patent incorporates a programmable delay circuit during the design phase that allows for preliminary timing adjustments. This enables timing optimization to be achieved in fewer iterations by providing direct control over clock timing parameters, thereby reducing the development schedule impact.
4Reliability
If signal lines are re-routed to avoid cross-coupling, then logic errors are reduced, but device complexity increases
Solution Approach 1:
The patent converts the potential harm of cross-coupling capacitance into a benefit by using programmable delay to stagger the switching times of adjacent signal lines. This approach reduces logic errors from glitches while avoiding the need for complex signal line re-routing, as the timing adjustment is achieved through clock signal manipulation rather than physical reconfiguration.
Data Source
AI summary
A circuit including a first stage register that operates in response to a first clock having a period TCYCLE, a programmable delay circuit that introduces a programmable delay to the first clock, thereby creating a second clock, a second stage register that operates in response to the second clock, combinational logic coupled between the first register output and the second register input, and a third register having an input coupled to the second register output. The programmable delay is selected: (1) to have a positive value if the signal delay between the first and second registers exceeds TCYCLE, and (2) such that the signal delay between the second and third registers is less than TCYCLE minus the programmable delay. Additional delayed clocks generated in response to the second clock signal can be used to operate additional second stage registers, thereby staggering the outputs of these second stage registers within TCYCLE.